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? 2014 microchip technology inc. ds20005334a-page 1 ucs81003 features: ? port power switch with two current limit behaviors - 2.9v to 5.5v source voltage range - up to 3.0a current (2.85a typical) with 55 m ? on resistance - overcurrent trip or constant current limiting - soft turn-on circuitry - programmable current limit - dynamic thermal management - under and overvoltage lockout - back-drive, back-voltage protection - latch or auto-recovery (low test current) fault handling - selectable active-high or -low power switch enable - bc1.2 v bus discharge port renegotiation function ? selectable/automatic cycling of universal serial bus (usb) data line charger emulation profiles - usb-if bc1.2 charging downstream port (cdp) and dedicated charging port (dcp) modes, chinese telecommunications industry standard yd/t 1591-2009 and most apple ? inc. and rim ? protocols standard; others as defined via the smbus 2.0/i 2 c ? protocol - supports 12w charging emulation - usb 2.0 compliant high-speed data switch (in data pass-through, sdp and cdp modes) - nine preloaded charger emulation profiles for maximum compatibility coverage of the peripheral devices - one custom-programmable charger emulation profile for portable device support for fully host-controlled charger emulation ? supports active cables ? self-contained current monitoring and rationing for power-allocation applications ? low-power attach detection and open-drain (a_det#) pin ? ultra-low power sleep state ? optional split supply support for v s and v dd for low-power in system standby states ? wake on attach usb ? smbus 2.0/i 2 c communications - supports block write and read - multiple smbus addresses ? wide operating temperature range: -40c to +85c ? iec61000-4-2 8/15 kv electrostatic discharge (esd) immunity description: the ucs81003 provides a usb port power switch for precise control of up to 3.0a continuous current (2.85a typical) with overcurrent limit (ocl), dynamic thermal management, latch or auto-recovery (low-test current) fault handling, selectable active-low or -high enable, under and overvoltage lockout, back-drive protection and back-voltage protection. split supply support for v s and v dd is an option for low power in system standby states. this gives battery- operated applications (such as on-board computers) the ability to detect attachments from a sleep or off state. after the attach detection is flagged, the system can decide to wake up and/or provide charging. in addition to power switching and current limiting modes, the ucs81003 will automatically charge a wide variety of portable devices, including usb-if bc1.2, yd/t-1591 (2009), most apple inc. and rim, and many others. nine preloaded charger emulation profiles maximize the compatibility coverage of the peripheral devices. additionally, a customizable charger emulation profile is available to accommodate unique existing and future portable device handshaking/signature requirements. the ucs81003 also provides current monitoring to allow intelligent management of system power and charge rationing for controlled delivery of current, regardless of the host power state. this is especially important for battery-operated applications that want to provide power and do not want to drain the battery excessively. the ucs81003 is available in a 5 mm x 5 mm 28-pin vqfn package. applications: ? dc power socket replacement ? consumer usb port protection ? consumer device charging port ? auxiliary box charging feature ? rear seat entertainment consumer access point automotive usb port power controller with charger emulation
ucs81003 ds20005334a-page 2 ? 2014 microchip technology inc. package type m2 v bus v s1 v s3 v s2 m1 nc v bus2 v bus3 pwr_en nc sel nc nc smdata/latch smclk/s0 alert# d pin d min em_en a_det# d pout d mout nc comm_sel/i lim v dd nc gnd 1 2 3 4 5 6 715 8 9 10 11 12 13 14 16 17 18 19 20 21 26 25 24 23 22 28 27 ep-29 * includes exposed thermal pad (ep); see ta b l e 3 - 1 . ucs81003 5x5vqfn*
? 2014 microchip technology inc. ds20005334a-page 3 ucs81003 block diagram charger control, measurement, ocl interface, logic comm_sel/i lim alert# a_det# pwr_en sel em_en m1 m2 smclk/s0 smdata/latch power switch temp d pout d mout d pin v dd v s v bus d min gnd usb 2.0 hs data switch & charger emulator attach detector v dd v dd uvlo, ovlo
ucs81003 ds20005334a-page 4 ? 2014 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd , v s and v bus pins ....................................................................................................................-0.3 t o 6v pull-up voltage (v pullup ) ................................................................................................................... -0.3 to v dd + 0.3v data switch current (i hsw_on ), switch on........................................................................................................... 50 ma port power switch current ..................................................................................................... ................ internally limited data switch pin voltage to ground (d pout , d pin , d mout , d min ); (v dd powered or unpowered)....... -0.3 to v dd +0.3v differential voltage across open data switch (d pout -d pin , d mout - d min , d pin - d pout , d min - d mout ) .............v dd voltage on any other pin to ground ............................................................................................ ....... -0.3 to v dd + 0.3v current on any other pin ....................................................................................................... ............................... 10 ma package power dissipation ...................................................................................................... ......................... ta b l e 1 - 1 maximum junction temperature under bias ........................................................................................ ................ +125c storage temperature range...................................................................................................... .............-55c to +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: power dissipation summary board package ? jc ? ja de-rating factor above +25c t a <+25c power rating t a <+70c power rating t a <+85c power rating high k (see note 1 ) 28-pin vqfn 5x5 mm 4c/w 32c/w 31.3 mw/c 2470 mw 1220 mw 800 mw low k (see note 1 ) 28-pin vqfn 5x5 mm 4c/w 51c/w 19.6 mw/c 1620 mw 800 mw 530 mw note 1: junction to ambient ( ? ja ) is dependent on the design of the thermal vias. without thermal vias and a ther- mal landing, the ? ja is approximately 77c/w, including localized pcb temperature increase. this ? ja value is an estimate for a jedec ? compliant 2s2p pcb with thermal vias. table 1-2: electrical characteristics electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions power supply supply voltage v dd 4.5 5 5.5 v note 1 source voltage v s 2.9 5 5.5 v note 1 supply current in active (i dd_active + i vs_act ) i active ? 650 750 a average current i bus =0ma, t j <+85c note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
? 2014 microchip technology inc. ds20005334a-page 5 ucs81003 supply current in sleep (i dd_sleep + i vs_sleep ) i sleep ? 5 15 a average current v pullup ? v dd , t j <+85c supply current in detect (i dd_detect + i vs_detect ) i detect ? 175 ? a average current, no portable device attached power-on reset v s low threshold v s_uvlo ?2.5? vv s voltage increasing v s low hysteresis v s_uvlo_hyst ?100? mvv s voltage decreasing v dd low threshold v dd_th ?4? vv dd voltage increasing v dd low hysteresis v dd_th_hyst ?500? mvv dd voltage decreasing i/o pins - smclk, smdata, em_en, m1, m2, pwr_en, s0, latch, alert#, a_det# ? dc parameters output low voltage v ol ??0.4 vi sink_io = 8 ma smdata, alert#, a_det# input high voltage v ih 2.1 ? ? v pwr_en, em_en, m1, m2, latch, s0, smdata, smclk input low voltage v il ? ? 0.8 v pwr_en, em_en, m1, m2, latch, s0, smdata, smclk leakage current i leak ? ? 5 a powered or unpowered, v pullup ? v dd , t j <+85c interrupt pins - ac parameters alert#, a_det# pin blanking time t blank ?25? ms alert# pin interrupt masking time t mask ?5?ms smbus/i 2 c? timing input capacitance c in ?5?pf clock frequency f smb 10 ? 400 khz spike suppression t sp ?50 ns note 2 bus free time stop to start t buf 1.3 ? ? s start setup time t su:sta 0.6 ? ? s start hold time t hd:sta 0.6 ? ? s stop setup time t su:sto 0.6 ? ? s data hold time t hd:dat 0 ? ? s when transmitting to the master data hold time t hd:dat 0.3 ? ? s when receiving from the master data setup time t su:dat 0.6 ? ? s clock low period t low 1.3 ? ? s clock high period t high 0.6 ? ? s table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
ucs81003 ds20005334a-page 6 ? 2014 microchip technology inc. clock/data fall time t fall ? ? 300 ns min = 20 + 0.1 c load ns, note 3 clock/data rise time t rise ? ? 300 ns min = 20 + 0.1 c load ns, note 3 capacitive load c load ? ? 400 pf per bus line, note 2 timeout t timeout 25 ? 35 ms disabled by default, note 2 idle reset t idle_reset 350 ? ? s disabled by default, note 2 high-speed data switch high-speed data switch - dc parameters switch leakage current i hsw_off ? 0.5 ? a switch open - d pin to d pout , d min to d mout , or all four pins to ground. v dd ? v s charger resistance r chg ?2?m ? d pout or d mout to v bus or ground (see figure 1-2 ), bc1.2 dcp charger emulation active on resistance r on_hsw ?2? ? switch closed, v dd = 5v test current = 8 ma, test voltage = 0.4v, see figure 1-2 on resistance r on_hsw_1 ?5? ? switch closed, v dd = 5v, test current = 8 ma, test voltage = 3.0v, see figure 1-2 delta-on resistance ? r on_hsw ?0.3? ? switch closed, v dd = 5v, i tst = 8 ma, v tst = 0 to 1.5v, see figure 1-2 high-speed data switch - ac parameters d p , d m capacitance to ground c hsw_on ? 4 ? pf switch closed, v dd = 5v d p , d m capacitance to ground c hsw_off ? 2 ? pf switch open, v dd = 5v turn off time t hsw_off ? 400 ? s time from state control (em_en, m1, m2) switch on to switch off, r term =50 ? , c load =5pf turn-on time t hsw_on ? 400 ? s time from state control (em_en, m1, m2) switch off to switch on, r term =50 ? , c load =5pf propagation delay t pd ?0.25? nsr term =50 ? , c load =5pf table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
? 2014 microchip technology inc. ds20005334a-page 7 ucs81003 propagation delay skew ? t pd ?25? psr term =50 ? , c load =5pf rise/fall time t f/r ?10? nsr term =50 ? , c load =5pf d p ? d m crosstalk x talk ?-40? dbr term =50 ? , c load =5pf off isolation o irr ?-30? dbr term =50 ? , c load =5pf, f= 240mhz -3 db bandwidth bw ? 1100 ? mhz r term =50 ? , c load =5pf, v dpout =v dmout =350mvdc to t a l j i t t e r t j ?200? psr term =50 ? , c load =5pf, rise time = fall time = 500 ps at 480 mbps (prbs = 2 15 ?1) skew of opposite transitions of the same output t sk(p) ?20? psr term =50 ? , c load =5pf port power switch port power switch - dc parameter overvoltage lockout v s_ov ?6? v on resistance r on_psw ?55?m ? 4.75v < v s < 5.25v v s leakage current i leak_vs ? 2.22 ? a sleep state into v s pin back-voltage protection threshold v bv_th ?150? mvv bus > v s , v s > v s_uvlo back-drive current i bd_1 ?0 3 av dd < v dd_th , any powered power pin to any unpowered power pin. current out of unpowered pin ( note 3 ). i bd_2 ?0 2 av dd < v dd_th , any powered power pin to any unpowered power pin, except for v dd to v bus in detect power state and v s to v bus in active power state. current out of unpowered pin ( note 3 ). table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
ucs81003 ds20005334a-page 8 ? 2014 microchip technology inc. selectable current limits i lim1 ?570? mai lim resistor = 0 or 47 k ? (minimum ma setting) i lim2 ? 1000 ? i lim resistor = 10 k ? or 56 k ? i lim3 ?1130? i lim resistor = 12 k ? or 68 k ? i lim4 ? 1350 ? i lim resistor = 15 k ? or 82 k ? i lim5 ? 1680 ? i lim resistor = 18 k ? or 100 k ? i lim6 ? 2050 ? i lim resistor = 22 k ? or 120 k ? i lim7 ? 2280 ? i lim resistor = 27 k ? or 150 k ? i lim8 ? 2850 3000 i lim resistor = 33 k ? or v dd pin wake time t pin_wake ?3?ms smbus wake time t smb_wake ?4?ms idle sleep time t idle_sleep ?200? ms thermal regulation limit t reg ? 110 ? c die temperature at which current limit will be reduced. thermal regulation hysteresis t reg_hyst ?10? chysteresis for t reg functionality. temperature must drop by this value before i lim value restored to normal operation. thermal shutdown threshold t tsd ? 135 ? c die temperature at which port power switch will turn off. thermal shutdown hysteresis t tsd_hyst ? 35 ? c after shutdown due to t tsd being reached, a die temperature drop is required before port power switch can be turned on again. auto-recovery test current i test ? 190 ? ma portable device attached, v bus = 0v, die temp < t tsd auto-recovery test voltage v test ? 750 ? mv portable device attached, v bus = 0v before application, die temp < t tsd programmable, 250 - 1000 mv, default listed discharge impedance r discharge ?100? ? table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
? 2014 microchip technology inc. ds20005334a-page 9 ucs81003 port power switch - ac parameters turn-on delay t on_psw ? 0.75 ? ms pwr_en active toggle to switch on time, v bus discharge not active. turn-off time t off_psw_ina ? 0.75 ? ms pwr_en inactive toggle to switch off time c bus = 120 f turn-off time t off_psw_err ? 1 ? ms overcurrent error, v bus min error, or discharge error to switch off, c bus = 120 f turn-off time t off_psw_err ? 100 ? ns tsd or back-drive error to switch off, c bus = 120 f v bus output rise time t r_bus ? 1.1 ? ms measured from 10% to 90% of v bus , c load = 220 f, i lim = 1.0a soft turn-on rate ? i bus / ? t ?100?ma/s temperature update time t dc_temp ? 200 ? ms programmable 200 - 1600 ms, default listed short-circuit response time t short_lim ? 1.5 ? s time from detection of short to current limit applied. no c bus applied. short-circuit detection time t short ? 6 ? ms time from detection of short to port power switch disconnect and alert# pin assertion. latched mode cycle time t ul ? 7 ? ms from pwr_en edge transition from inactive to active to begin error recovery. auto-recovery mode cycle time t cycle ? 25 ? ms time delay before error condition check. programmable 10-25 ms, default listed. auto-recovery delay t rst ? 20 ? ms portable device attached, v bus must be ? v test after this time. programmable 10-25 ms, default listed. discharge time t discharge ? 200 ? ms amount of time discharge resistor applied. programmable 100-400 ms, default listed. table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
ucs81003 ds20005334a-page 10 ? 2014 microchip technology inc. port power switch operation with trip mode current limiting region 2 current keep-out i bus_r2min ?0.12? a minimum v bus allowed at output v bus_min 1.5 2.0 2.25 v note 5 port power switch operation with constant current limiting (variable slope) region 2 current keep-out i bus_r2min ?1.68? a minimum v bus allowed at output v bus_min 1.5 2.0 2.25 v note 5 current measurement - dc current measurement range i bus_m 0 ? 2988.6 ma range 0 ? 255 lsb (see note 4 ) reported current measurement resolution d ibus_m ? 11.72 ? ma 1 lsb current measurement accuracy ? 2 ? % 180 ma < i bus < i lim ?2?lsbi bus < 180 ma current measurement - ac sampling rate ? 500 ? s charge rationing - dc accumulated current measurement accuracy ?4.5? % charge rationing - ac current measurement update time t pcycle ?1? s attach/removal detection v bus bypass - dc on resistance r on_byp ?50? ? leakage current i leak_byp ? ? 3 a switch off, t a <+85c, note 2 current limit i de- t_chg /i bus_by p ?2?mav dd = 5v and v bus > 4.75v attach/removal detection - dc attach detection threshold i det_qual ? 800 ? a programmable 200 ? 1000 a, default listed. table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
? 2014 microchip technology inc. ds20005334a-page 11 ucs81003 primary removal detection threshold i rem_qual_act ? 700 ? a programmable 100 ? 900 a, default listed, active power state ? 800 ? a programmable 200 ? 1000 a, default listed, detect power state (see section 8.4 ?removal detection? ). attach/removal detection - ac attach detection time t det_qual ? 100 ? ms time from attach to a_det# assert removal detection time t rem_qual ? 1000 ? ms allowed charge time t det_charge ?800? msc bus = 500 f maximum, programmable 200 ? 2000 ms, default listed. charger emulation profile general emulation - dc charging current threshold i bus_chg ?175.8? madefault charging current threshold range i bus_chg_rng 11.72 ? 175.8 ma note 5 dp-dm shunt resistor value r dcp_res ? 200 ? connected between d pout and d mout , 0v < d pout = d mout < 3v response magnitude (voltage divider option resistance range) sx_rxmag_dvdr 93 ? 200 k ? note 5 resistor ratio range (voltage divider option) sx_ratio 0.25 ? 0.66 v/v note 5 resistor ratio accuracy (voltage divider option) sx_ratio_ acc ? 0.5 ? % average over range response magnitude (resistor option range) sx_rxmag_res 1.8 ? 150 k ? note 5 internal resistor tolerance (resistor option) sx_rxmag_res _acc ? 10 ? % average over range response magnitude (voltage option range) sx_rxmag_volt 0.4 ? 2.2 v note 5 voltage option accuracy sx_rxmag_volt _acc ? 1 ? % no load, average over range voltage option accuracy sx_rxmag_volt _acc_ 150 ? -6 ? % 150 a load, average over range voltage option accuracy sx_rxmag_volt _acc_ 250 ? -10 ? % 250 a load, average over range table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
ucs81003 ds20005334a-page 12 ? 2014 microchip technology inc. figure 1-1: usb rise time/fall time measurement. voltage option output sx_rxmag_volt _bc 0.5 ? ? v d mout = 0.6v, 250 a load, note 3 response magnitude (zero volt option range) sx_pupd 10 ? 150 a sx_rxmag_volt = 0 note 5 pull-down current accuracy sx_pupd _acc_3p6 ?5? %d pout or d mout = 3.6v compliance voltage pull-down current sx_pupd _acc_bc 50 ? ? a setting = 100 a d pout or d mout = 0.15v compliance voltage, note 3 stimulus voltage threshold range sx_th 0.3 ? 2.2 v note 5 stimulus voltage accuracy sx_th_ acc ? 2 ? % average over range stimulus voltage accuracy sx_th_acc_bc 0.25 ? ? v at sx_th = 0.3v, note 3 general emulation - ac emulation reset time t em_reset ?50? msdefault emulation reset time range t em_reset_ rng 50 ? 175 ms note 5 emulation timeout range t em_ timeout 0.8 ? 12.8 s note 5 stimulus delay, sx_td range t stim_del 0 ? 100 ms note 5 emulation delay t res_em ? ? 0.5 s time from set impedance to impedance appears on d p /d m , note 3 . table 1-2: electrical characteristics (continued) electrical characteristics: unless otherwise specified, v dd = 4.5v to 5.5v, v s = 2.9v to 5.5v, v pullup = 3v to 5.5v, t j = -40c to +125c; all typical values at v dd = v s = 5v, t j = +27c. characteristic sym. min. typ. max. unit conditions note 1: for split supply systems using the attach detection feature, v s must not exceed v dd +150mv. 2: this parameter is ensured by design and is not 100% tested. 3: this parameter is characterized, but not 100% production tested. 4: the current measurement full-scale range maximum value is 3.0a. however, the ucs81003 cannot report values above i lim (if i bus_r2min ? i lim ) or above i bus_r2min (if i bus_r2min > i lim and i lim ?? 1.68a). 5: the minimum and maximum values represent the boundaries of a programmable range. each value in the range is typical.
? 2014 microchip technology inc. ds20005334a-page 13 ucs81003 figure 1-2: description of dc terms. table 1-3: temperature specifications parameters sym. min. typ. max. units conditions temperature ranges operating temperature range t a -40 ? +85 c storage temperature range t a -55 ? +150 c thermal package resistances - see table 1-1 d pin d pout r chg v bus v tst r chg i tst d min r chg v bus v tst r chg i tst d mout
ucs81003 ds20005334a-page 14 ? 2014 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, v dd = v s = 5v, t j = +27c . figure 2-1: usb-if high-speed eye diagram (without data switch). figure 2-2: usb-if high-speed eye diagram (with data switch). figure 2-3: short applied after power-up. figure 2-4: power-up into a short. figure 2-5: internal power switch short response. figure 2-6: v bus discharge behavior. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -1 0 1 2 3 4 5 6 -1 0 1 2 3 4 5 6 0246810 current (a) voltage (v) time (ms) v s = v dd = 5v i lim = 3a max. (2.85a typical), short applied at 2 ms alert # i bus v bus 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 5 010203040 50 v dd alert# pin i bus current time (ms) voltage (v) current (a) voltage (v) v s =v dd = 5v, short applied at 16 ms -2 -1 0 1 2 3 4 5 6 02040 -2 0 2 4 6 8 10 12 14 voltage (v) time (s) current (a) v s =v dd = 5v, i lim = 2.05a (typical), short applied at 17.2 s v bus i bus -1 0 1 2 3 4 5 6 0 100 200 300 400 500 voltage (v) time (ms) v bus em_en v s = v dd = 5v m2 = 0, m1 = pwr_en = 1
? 2014 microchip technology inc. ds20005334a-page 15 ucs81003 note: unless otherwise indicated, v dd = v s = 5v, t j = +27c . figure 2-7: data switch off isolation vs. frequency. figure 2-8: data switch bandwidth vs. frequency. figure 2-9: data switch on resistance vs. temperature. figure 2-10: power switch on resistance vs. temperature. figure 2-11: r dcp_res resistance vs.temperature. figure 2-12: power switch on/off time vs. temperature. 0 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 100 1000 off isolation (db) frequency (mhz) d pout = d mout = 0.35v -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0.01 1 100 10000 gain (db) frequency (mhz) d pout = d mout = 0.35v 0.0 0.5 1.0 1.5 2.0 2.5 -40 -15 10 35 60 85 on resistance ( : ) temperature (c) d pout = d mout = 0.4v 0 10 20 30 40 50 60 70 -40 -15 10 35 60 85 on resistance (m : ) temperature (c) 0 20 40 60 80 100 120 140 160 180 200 -40 -15 10 35 60 85 resistance ( : ) temperature (c) d pout = d mout = 3v d pout = d mout = 0.15v 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 -40 -15 10 35 60 85 time (ms) temperature (c) v s = v dd = 5v turn off time turn on time
ucs81003 ds20005334a-page 16 ? 2014 microchip technology inc. note: unless otherwise indicated, v dd = v s = 5v, t j = +27c . figure 2-13: v s overvoltage threshold vs. temperature. figure 2-14: v s undervoltage threshold vs. temperature. figure 2-15: detect state v bus vs. i bus . figure 2-16: trip current limit operation vs. temperature. figure 2-17: i bus measurement accuracy. figure 2-18: active state current vs. temperature. 5.9 5.91 5.92 5.93 5.94 5.95 5.96 5.97 5.98 5.99 6 -40 -15 10 35 60 85 threshold voltage (v) temperature (c) v dd = 5v 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 -40 -15 10 35 60 85 v s threshold voltage (v) temperature (c) threshold hysteresis v dd = 5v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 500 1000 1500 2000 2500 3000 3500 4000 voltage (v) current (a) v s = v dd = 5v s0 = '1' pwr_en disabled -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -40 -15 10 35 60 85 current limit accuracy temperature (c) v s = v dd = 5v i lim = 3.0 a max. (2.85a typical) note: specification is 0% maximum and -10% minimum -5 -4 -3 -2 -1 0 1 2 3 4 5 00.511.522.53 accuracy (%) current (a) v s = v dd = 5v 0 100 200 300 400 500 600 700 800 -40 -15 10 35 60 85 $fwlyh current (a) temperature (c) i dd v s = v dd = 5v i dd + i s i s
? 2014 microchip technology inc. ds20005334a-page 17 ucs81003 note: unless otherwise indicated, v dd = v s = 5v, t j = +27c . figure 2-19: detect state current vs. temperature. figure 2-20: sleep state current vs. temperature. 0 50 100 150 200 250 -40 -15 10 35 60 85 detect current (a) temperature (c) i dd v s = v dd = 5v i dd + i s i s 0 1 2 3 4 5 6 7 8 9 10 -40 -15 10 35 60 85 sleep current (a) temperature (c) i dd v s = v dd = 5v i dd + i s i s
? 2014 microchip technology inc. ds20005334a-page 18 ucs81003 3.0 pin description the description of the pins are listed in table 3-1 . table 3-1: pin function table ucs81003 5x5 vqfn symbol function pin type connection type if pin not used 1 nc not internally connected n/a leave open 2 m1 active mode selector input #1 di connect to ground or v dd (see note 3 ) 3 m2 active mode selector input #2 di connect to ground or v dd (see note 3 ) 4v bus1 voltage output from power switch. these pins are internally connected and must be tied together. hi-power note 1 leave open 5v bus2 6v bus3 7 comm_sel/i lim comm_sel - selects smbus or stand-alone mode of operation (see table 11-1 ). aio n/a i lim - selects the hardware current limit at power-up. 8 sel selects polarity of pwr_en control and smbus address (see ta b l e 11 - 2 ). aio n/a 9v s1 voltage input to power switch. these pins are internally connected and must be tied together. hi-power connect to ground 10 v s2 11 v s3 12 v dd main power supply input for chip functionality power n/a 13 pwr_en port power switch enable input. polarity determined by sel pin. di connect to ground or v dd (see note 3 ) 14 nc not internally connected n/a leave open 15 nc not internally connected n/a leave open note 1: total leakage current from pins 4, 5 and 6 (v bus ) to ground must be less than 100 a for proper attach/removal detection operation. 2: it is recommended to use 2 m ? pull-down resistors on the d pout and/or d mout pin if a portable device stimulus is expected when using the customer charger emulation profile with t he high-speed data switch open. the 2 m ? value is based on bc1.1 impedance characteristics for dedicated charging ports. 3: to ensure operation, the pwr_en pin must be enabled, as determined by the sel pin decode, when it is not driven by an external device. furthermore, one of the m1, m2 or em_en pins must be connected to v dd if all three are not driven from an external device. if the pwr_en pin is disabled or all of the m1, m2 and em_en pins are connected to ground, the ucs81003 will remain in the sleep or detect state unless activated via the s mbus.
ucs81003 ds20005334a-page 19 ? 2014 microchip technology inc. 16 smdata/latch smdata - smbus data input/output (requires pull-up resistor) diod n/a latch - in stand-alone mode, latch/auto-recovery fault handling mechanism selection input (see section 7.5 ?fault handling mechanism? ) di 17 smclk/s0 smclk - smbus clock input (requires pull-up resistor) di n/a s0 - in stand-alone mode, enables attach/removal detection feature (see section 5.3.6 ?s0 input? ) 18 alert# active low error event output flag (requires pull-up resistor) od connect to ground 19 d pin usb data input (plus) aio connect to ground or ground through a resistor 20 d min usb data input (minus) aio connect to ground or ground through a resistor 21 nc not internally connected n/a leave open 22 nc not internally connected n/a leave open 23 d mout usb data output (minus) aio (see note 2 ) connect to ground 24 d pout usb data output (plus) aio (see note 2 ) connect to ground 25 a_det# active low device attach detection output flag (requires pull-up resistor) od connect to ground 26 em_en active mode selector input di connect to ground or v dd (see note 3 ) 27 gnd ground power n/a 28 nc not internally connected n/a leave open 29 ep exposed thermal pad. must be connected to the electrical ground. ep n/a table 3-1: pin function table ucs81003 5x5 vqfn symbol function pin type connection type if pin not used note 1: total leakage current from pins 4, 5 and 6 (v bus ) to ground must be less than 100 a for proper attach/removal detection operation. 2: it is recommended to use 2 m ? pull-down resistors on the d pout and/or d mout pin if a portable device stimulus is expected when using the customer charger emulation profile with t he high-speed data switch open. the 2 m ? value is based on bc1.1 impedance characteristics for dedicated charging ports. 3: to ensure operation, the pwr_en pin must be enabled, as determined by the sel pin decode, when it is not driven by an external device. furthermore, one of the m1, m2 or em_en pins must be connected to v dd if all three are not driven from an external device. if the pwr_en pin is disabled or all of the m1, m2 and em_en pins are connected to ground, the ucs81003 will remain in the sleep or detect state unless activated via the s mbus.
ucs81003 ds20005334a-page 20 ? 2014 microchip technology inc. table 3-2: pin types description pin type description power this pin is used to supply power or ground to the device hi-power this pin is a high-current pin aio analog input/output - this pin is used as an i/o for analog signals. di digital input - this pin is used as a digital input. this pin will be glitch-free. diod open-drain digital input/output - this pin is bidirectional. it is open-drain and requires a pull-up resistor. this pin will be glitch-free. od open-drain digital output - used as a digital output. it is open-drain and requires a pull-up resistor. this pin will be glitch-free. ep exposed thermal pad
? 2014 microchip technology inc. ds20005334a-page 21 ucs81003 4.0 terms and abbreviations note: the m1, m2, pwr_en and em_en pins each have configuration bits (_set in section 10.4.3 ?switch configuration register? ) that may be used to perform the same function as the external pin state. these bits are accessed via the smbus/i 2 c and are or?d with the respective pin. this or?d combination of pin state and register bit is referenced as the control. table 4-1: terms and abbreviations term/abbreviation description active mode active power state operation mode: data pass-through, bc1.2 sdp, bc1.2 cdp, bc1.2 dcp or dedicated charger emulation cycle. attach detection an attach detection event occurs when the current drawn by a portable device is greater than i det_qual for longer than t det_qual . attachment the physical insertion of a portable device into a usb port that ucs81003 is controlling. cc constant current cdm charged device model. jedec ? model for characterizing susceptibility of a device to damage from esd. cdp or usb-if bc1.2 cdp charging downstream port. the combination of the ucs81003 cdp handshake and an active standard usb host comprises a cdp. this enables a bc1.2 compliant portable device to simultaneously draw current up to 1.5a while data communication is active. the usb high-speed data switch is closed in this mode. charge enable when a charger emulation profile has been accepted by a portable device and charging commences. charger emulation profile representation of a charger comprised of d pout , d mout and v bus signaling, which make up a defined set of signatures or handshaking protocols. connection usb-if term which refers to establishing active usb communications between a usb host and a usb device. current limiting mode determines the action that is performed when the i bus current reaches the i lim threshold. trip opens the port power switch. constant current (variable slope) allows v bus to be dropped by the portable device. dce dedicated charger emulation. charger emulation in which the ucs81003 can deliver power only (by default). no active usb data communication is possible when charging in this mode (by default). dcp or usb-if bc1.2 dcp dedicated charging port. this functions as a dedicated charger for a bc1.2 portable device. this allows the portable device to draw currents up to 1.5a with constant current limiting (and beyond 1.5a with trip current limiting). no usb communications are possible (by default). dc dedicated charger. a charger which inherently does not have usb communications, such as an a/c wall adapter. disconnection usb-if term which refers to the loss of active usb communications between a usb host and a usb device. dynamic thermal management the ucs81003 automatically adjusts port power switch limits and modes to lower internal power dissipation when the thermal regulation temperature value is approached. enumeration a usb-specific term indicating that a host is detecting and identifying usb devices. handshake application of a charger emulation profile that requires a response. two-way communication between the ucs81003 and the portable device. hbm human body model hsw high-speed switch i bus_r2min current limiter mode boundary
ucs81003 ds20005334a-page 22 ? 2014 microchip technology inc. i lim the i bus current threshold used in current limiting. in trip mode, when i lim is reached, the port power switch is opened. in constant current mode, when the current exceeds i lim , oper- ation continues at a reduced voltage and increased current; if v bus voltage drops below v bus_min , the port power switch is opened. legacy usb devices that require non-bc1.2 signatures be applied on the d pout and d mout pins to enable charging. ocl overcurrent limit por power-on reset portable device usb device attached to the usb port. power thief a usb device that does not follow the handshaking conventions of a bc1.2 device or legacy devices and draws current immediately upon receiving power (i.e., a usb book light, portable fan, etc). removal detection a removal detection event occurs when the current load on the v bus pin drops to less than i rem_qual for longer than t rem_qual . removal the physical removal of a portable device from a usb port that the ucs81003 is controlling. response an action, usually in response to a stimulus, in charger emulation performed by the ucs81003 device via the usb data lines. sdp or usb-if sdp standard downstream port. the combination of the ucs81003 high-speed switch being closed with an upstream usb host present comprises a bc1.2 sdp. this enables a bc1.2 compliant portable device to simultaneously draw current up to 0.5a while data communica- tion is active. signature application of a charger emulation profile without waiting for a response. one-way communi- cation from the ucs81003 to the portable device. stand-alone mode indicates that the communications protocol is not active and all communications between the ucs81003 and a controller are done via the external pins only (m1, m2, em_en, pwr_en, s0 and latch as inputs, and alert# and a_det# as outputs). stimulus an event in charger emulation detected by the ucs81003 device via the usb data lines. table 4-1: terms and abbreviations (continued) term/abbreviation description
? 2014 microchip technology inc. ds20005334a-page 23 ucs81003 5.0 general description the ucs81003 provides a single usb port power switch for precise control of up to 3.0a continuous current with overcurrent limit (ocl), dynamic thermal management, latch or auto-recovery fault handling, selectable active-low or -high enable, under and overvoltage lockout, and back-voltage protection. split supply support for v bus and v dd is an option for low power in system standby states. in addition to power switching and current limiting, the ucs81003 provides automatic and configurable charger emulation profiles to charge a wide variety of portable devices, including usb-if bc1.2 (cdp or dcp modes), yd/t-1591 (2009), 12w charging, most apple and rim portable devices and many others. the ucs81003 also provides current monitoring to allow intelligent management of system power and charge rationing for controlled delivery of current regardless of the host power state. this is especially important for battery-operated applications that need to provide power without excessively draining the battery, or that require power allocation depending on application activities. figure 5-1 shows a ucs81003 full-featured system configuration in which the ucs81003 provides a port power switch and low-power attach detection with wake-up signaling (wake on usb). the current limit is established at power-up. it can be lowered if required after power-up via the smbus/i 2 c. this configuration also provides configurable usb data line-charger emulation, programmable current limiting (as determined by the accepted charger emulation profile), active current monitoring and port charge rationing. figure 5-1: ucs81003 system configuration (with charger emulation, smbus control and usb host). ucs81003 alert# 3v C 5.5v device d pout d mout 5v v s1 v s2 a_det# 5v host c bus usb host 3v C 5.5v ec c in v dd d pin d min v dd em_en m1 m2 pwr_en smdata smclk sel comm_sel /i lim gnd v dd v s3 v bus1 v bus2 v bus3
ucs81003 ds20005334a-page 24 ? 2014 microchip technology inc. figure 5-2 shows a system configuration in which the ucs81003 provides a usb data switch, port power switch, low-power attach detection and portable device attach/removal detection signaling. this configuration does not include configurable data line charger emulation, programmable current limiting or current monitoring and rationing. figure 5-2: ucs81003 system configuration (charger emulation, no smbus, with usb host). ucs81003 latch alert# pwr_en 3v C 5.5v gnd device d pin d min d pout d mout v dd 5v v bus1 v bus2 v s1 v s2 comm_sel/i lim 3v C 5.5v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5v host c bus usb host s0 disable detect state enable detect state c in v s3 v bus3
? 2014 microchip technology inc. ds20005334a-page 25 ucs81003 figure 5-3 shows a system configuration in which the ucs81003 provides a port power switch, low-power attach detection and portable device attachment detected signaling. this configuration is useful for applications that already provide usb bc1.2 and/or legacy data line handshaking on the usb data lines, but still require port power switching and current limiting. figure 5-3: ucs81003 system configuration (no smbus, no charger emulation). ucs81003 alert# pwr_en 3v C 5.5v gnd device d pin d min d pout d mout v dd 5v v bus1 v bus2 v s1 v s2 latch s0 comm_sel/i li m 3v C 5.5v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5v host c bus usb host (dp, dm) disable detect state enable detect state c in v bus3 v s3
ucs81003 ds20005334a-page 26 ? 2014 microchip technology inc. figure 5-4 shows a system configuration in which the ucs81003 provides a port power switch, low-power attach detection, charger emulation (with no usb host) and portable device attachment detected signaling. this configuration is useful for wall adapter-type applications and cigarette-plug adapters. figure 5-4: ucs81003 system configuration (no smbus, no usb host, with charger emulation). 5.1 ucs81003 power states the ucs81003 has the following power states: ucs81003 latch alert# pwr_en 3v C 5.5v gnd device d pin d min d pout d mout v dd 5v v bus1 v bus2 v s1 v s2 s0 comm_sel/i lim 3v C 5.5v auto-recovery upon fault latch upon fault em_en m1 m2 sel a_det# 5v c bus disable detect state enable detect state c in v bus3 v s3 n n table 5-1: power states description state description off this power state is entered when the voltage at the v dd pin voltage is < v dd_th . in this state, the device is considered ?off?. the ucs81003 will not retain its digital states and register contents, nor respond to smbus/i 2 c communications. the port power switch, bypass switch and the high-speed data switches will be off. see section 5.1.1 ?off state operation? . sleep this is the lowest power state available. while in this state, the ucs81003 will retain digital functionality, respond to changes in emulation controls and wake to respond to smbus/i 2 c communications. the high- speed switch and all other functionality will be disabled. see section 5.1.2 ?sleep state operation? . detect this is a low-current power state. in this state, the device is actively looking for a portable device to be attached. the high-speed switch is disabled by default. while in this state, the ucs81003 will retain the configuration and charge rationing data, but it will not monitor the bus current. smbus/i 2 c communications will be fully functional. see section 5.1.3 ?detect state operation? . error this power state is entered when a fault condition exists. see section 5.1.5 ?error state operation? . active this power state provides full functionality. while in this state, operations include activation of the port power switch, usb data line handshaking/charger emulation and current limiting and charge rationing. see section 5.1.4 ?active state operation? .
? 2014 microchip technology inc. ds20005334a-page 27 ucs81003 table 5-2 shows the settings for the various power states, except off and error. if v dd v s_uvlo enabled 1 all ? 0b no ? high-speed switch disabled (by default). ? automatic transition to active state when conditions met (see section 5.1.3.1 ?automatic transition from detect to active? ). active (see section 9.0 ?active state? ) > v s_uvlo enabled 0 all ? 0b n/a ? high-speed switch enabled/disabled based on mode. ? port power switch is on at all times. ? attach and removal detection disabled. see note 2 . > v s_uvlo enabled 1 all ? 0b yes ? port power switch is on. ? removal detection enabled. note 1: in order to transition from active state data pass-through mode into sleep with these settings, change the m1, m2 and em_en pins before changing the pwr_en pin. see section 9.4 ?data pass-through (no charger emulation)? . 2: if s0 = ? 0 ? and a portable device is not attached in dce cycle mode, the ucs81003 will be cycling through charger emulation profiles (by default). there is no guarantee which charger emulation profile will be applied first when a portable device attaches.
ucs81003 ds20005334a-page 28 ? 2014 microchip technology inc. 5.1.1 off state operation the device is in the off state if v dd is less than v dd_th . when the ucs81003 is in the off state, it does nothing, and all circuitry is disabled. digital register values are not stored and the device will not respond to smbus commands. 5.1.2 sleep state operation when the ucs81003 is in the sleep state, the device is in its lowest-power state. the high-speed switch, bypass switch and the port power switch are disabled. the attach and removal detection feature is disabled. v bus will be near ground potential. the alert# pin is not asserted. if asserted prior to entering the sleep state, the alert# pin will be released. the a_det# pin is released. smbus activity is limited to single byte read or write. the first data byte read from the ucs81003 when in the sleep state will wake the device; however, the data to be read will return all 0 ?s and should be considered invalid. this is a ?dummy? read byte meant to wake the ucs81003. subsequent read or write bytes will be accepted normally. after the dummy read, the ucs81003 will be in a higher-power state (see figure 5-6 ). the device will return to sleep after the last communication, or if no further communication has occurred. figure 5-5 shows timing diagrams for waking the ucs81003 via external pins. figure 5-6 shows the timing for waking the ucs81003 via smbus. figure 5-5: wake timing via external pins. figure 5-6: wake via smbus read with s0 = ? 0 ?. m1 or m2 port power switch closed (active state) t pin_wake wake with m1 or m2 to active state data pass-through mode (pwr_en enabled, s0 = 0 ,em_en= 0 ,v s >v s_uvlo ) s0 bypass switch closed (detect state) t pin_wake wake with s0 (v s >v s_uvlo ,m1&m2&em_ en not all 0 and not set to data pass-through) 0101_111 0 a invalid data np smbus read a 0001_0000 0101_111 0 a valid data np 0001_0000 s s t idle_sleep sleep sleep dummy read returns invalid data and places device in temporary active state read returns valid data 0101_111 1 a s 0101_111 1 a s a power state temporary active state (not all functionality available) t smb_wake
? 2014 microchip technology inc. ds20005334a-page 29 ucs81003 5.1.3 detect state operation when the ucs81003 is in the detect state, the port power switch will be disabled. the high-speed switch is also disabled by default. the v bus output will be connected to the v dd voltage by a secondary bypass switch (see section 8.0 ?detect state? ). there is one non-recommended configuration which places the ucs81003 in the detect state, but v bus will not be discharged and a portable device attachment will not be detected. for the recommended configurations, see tab l e 5 - 2 . there are two methods for transitioning from the detect state to the active state: automatic and host-controlled. 5.1.3.1 automatic transition from detect to active for the detect state, set s0 to ? 1 ?, enable pwr_en, set the em_en, m1 and m2 controls to the desired active mode ( table 9-1 ), and supply v s >v s_uvlo . when a portable device is attached and an attach detection event occurs, the ucs81003 will automatically transition to the active state and operate according to the selected active mode. 5.1.3.2 host-controlled transition from detect to active for the detect state, set s0 to ? 1 ?, set the em_en, m1 and m2 controls to the desired active mode ( table 9-1 ), and configure one of the following: ? disable pwr_en and supply v s , or ? enable pwr_en and don?t supply v s . when a portable device is attached and an attach detection event occurs, the host must respond to transition to the active state. depending on the control settings in the detect state, this could entail: ? enabling pwr_en or ? supplying v s above the threshold. 5.1.3.3 state change from detect to active when conditions cause the ucs81003 to transition from the detect state to the active state, the following occurs: 1. the attach detection feature will be disabled; the removal detection feature remains enabled, unless s0 is changed to ? 0 ?. 2. the bypass switch will be turned off. 3. the discharge switch will be turned on briefly for t discharge . 4. the port power switch will be turned on. 5.1.4 active state operation every time that the ucs81003 enters the active state and the port power switch is closed, it will enter the mode as instructed by the host controller (see section 9.0 ?active state? ). the ucs81003 cannot be in the active state (and therefore, the port power switch cannot be turned on) if any of the following conditions exist: ?v s ucs81003 ds20005334a-page 30 ? 2014 microchip technology inc. when using the latch fault handler and the user has re-activated the device by clearing the err bit (see section 10.3 ?status registers? ), or toggling the pwr_en control, the ucs81003 will check that all of the error conditions have been removed. if using auto- recovery fault handler, after the t cycle time period, the ucs81003 will check that all of the error conditions have been removed. if all of the error conditions have been removed, the ucs81003 will return to the active state or detect state, as applicable. returning to the active state will cause the ucs81003 to restart the selected mode (see section 9.2 ?active mode selection? ). if the device is in the error state and a removal detection event occurs, it will check the error conditions and then return to the power state defined by the pwr_en, m1, m2, em_en and s0 controls. 5.2 supply voltages 5.2.1 v dd supply voltage the ucs81003 requires 4.5v to 5.5v present on the v dd pin for core device functionality. core device functionality consists of maintaining register states, wake-up upon smbus/i 2 c query and attach detection. 5.2.2 v s source voltage v s can be a separate supply and can be greater than v dd to accommodate high-current applications in which current path resistances result in unacceptable voltage drops that may prevent optimal charging of some portable devices. 5.2.3 back-voltage detection whenever the following conditions are true, the port power switch will be disabled, the v bus bypass switch will be disabled, the high-speed data switch will be disabled, and a back-voltage event will be flagged. this will cause the ucs81003 to enter the error power state (see section 5.1.5 ?error state operation? ). ?the v bus voltage exceeds the v s voltage by v bv_th and the port power switch is closed. the port power switch will be opened immediately. if the condition lasts for longer than t mask , then the ucs81003 will enter the error state. otherwise, the port power switch will be turned on as soon as the condition is removed. ?the v bus voltage exceeds the v dd voltage by v bv_th and the v bus bypass switch is closed. the bypass switch will be opened immediately. if the condition lasts for longer than t mask , then the ucs81003 will enter the error state. otherwise, the bypass switch will be turned on as soon as the condition is removed. 5.2.4 back-drive current protection if a self-powered portable device is attached, it may drive the v bus port to its power supply voltage level; however, the ucs81003 is designed such that leakage current from the v bus pins to the v dd or v s pins shall not exceed i bd_1 (if the v dd voltage is zero) or i bd_2 (if the v dd voltage exceeds v dd_th ). 5.2.5 undervoltage lockout on v s the ucs81003 requires a minimum voltage (v s_uvlo ) be present on the v s pin for active power state. 5.2.6 overvoltage detection and lockout on v s the ucs81003 port power switch will be disabled if the voltage on the v s pin exceeds a voltage (v s_ov ) for longer than the specified time (t mask ). this will cause the device to enter the error state. 5.3 discrete input pins 5.3.1 comm_sel/i lim input the comm_sel/i lim input determines the initial i lim settings and the communications mode, as shown in table 11-1 . 5.3.2 sel input the sel pin selects the polarity of the pwr_en control. in addition, if the ucs81003 is not configured to operate in stand-alone mode, the sel pin determines the smbus address. see table 11-2 . the sel pin state is latched upon device power-up and further changes will have no effect. 5.3.3 m1, m2 and em_en inputs the m1, m2 and em_en input controls determine the active mode and affect the power state (see table 5-2 and tab l e 9 - 1 ). when these controls are all set to ? 0 ? and pwr_en is enabled, the ucs81003 attach and removal detection feature is disabled. in smbus mode, the m1, m2 and em_en pin states will be ignored by the ucs81003 if the pin_ign configuration bit is set (see section 10.4.3 ?switch configuration register? ); otherwise, the m1_set, m2_set and em_en_set configuration bits (see section 10.4.3 ?switch configuration register? ) are checked along with the pins. note: if it is necessary to connect any of the control pins except the comm_sel/i lim or sel pins via a resistor to v dd or gnd, the resistor value should not exceed 100 k ? in order to meet the v ih and v il specifications.
? 2014 microchip technology inc. ds20005334a-page 31 ucs81003 5.3.4 pwr_en input the pwr_en control enables the port power switch to be turned on if conditions are met and affects the power state (see table 5-2 ). the port power switch cannot be closed if pwr_en is disabled. however, if pwr_en is enabled, the port power switch is not necessarily closed (see section 5.1.4 ?active state operation? ). polarity is controlled by the sel pin. in smbus mode, the pwr_en pin state will be ignored by the ucs81003 if the pin_ign configuration bit is set (see section 10.4.3 ?switch configuration register? ); otherwise, the pwr_ens configuration bit (see section 10.4.3 ?switch configuration register? ) is checked along with the pin. 5.3.5 latch input the latch input control determines the behavior of the fault handling mechanism (see section 7.5 ?fault handling mechanism? ). when the ucs81003 is configured to operate in stand- alone mode (see section 11.3 ?stand-alone operating mode? ), the latch control is available exclusively via the latch pin (see table 11-10 ). when the ucs81003 is configured to operate in smbus mode, the latch control is available exclusively via the latchs configuration bit (see section 10.4.3 ?switch configuration register? ). 5.3.6 s0 input the s0 control enables the attach and removal detection feature and affects the power state (see table 5-2 ). when s0 is set to ? 1 ?, an attach detection event must occur before the port power switch can be turned on (this statement requires pwr_en_beh otp bit is set to ? 1 ?). when s0 is set to ? 0 ?, the attach and removal detection feature is not enabled. when the device is configured to operate in smbus mode (see section 11.3 ?stand-alone operating mode? ), the s0 control is available exclusively via the s0_set configuration bit (see section 10.4.3 ?switch configuration register? ). otherwise, the s0 control is available exclusively via the s0 pin since the smbus protocol will be disabled. 5.4 discrete output pins 5.4.1 alert# and a_det# output pins the alert# pin is an active low open-drain interrupt to the host controller. the alert# pin is asserted (by default - see alert_mask in section 10.4.1 ?general configuration register? ) when an error occurs (see register 10-3 ). the alert# pin can also be asserted when the low_cur (portable device is pulling less current and may be finished charging) or treg (thermal regulation temperature exceeded) bits are set and linked. as well, when charge rationing is enabled, the alert# pin is asserted by default when the current rationing threshold is reached (as determined by ration_beh<1:0> - see tab le 7 - 1 ). the alert# pin is released when all error conditions that may assert the alert# pin (such as an error condition, charge rationing, and treg and low_chg if linked) have been removed or reset as necessary. the a_det# pin provides an active-low open-drain output indication that a valid attach detection event has occurred. it will remain asserted until the ucs81003 is placed into the sleep state or a removal detection event occurs. for wake on usb, the a_det# pin assertion can be utilized by the system. if the s0 control is ? 0 ? and the ucs81003 is in the active state, the a_det# pin will be asserted regardless if a portable device is attached or not. if s0 is ' 1 ', pwr_en is enabled and v s is not present, the a_det# pin will cycle if the current draw exceeds the current capacity of the bypass switch. 5.4.2 interrupt blanking the alert# and a_det# pins will not be asserted for a specified time (up to t blank ) after power-up. additionally, an error condition (except for the thermal shutdown) must be present for longer than a specified time (t mask ) before the alert# pin is asserted.
ucs81003 ds20005334a-page 32 ? 2014 microchip technology inc. 6.0 usb high-speed data switch the ucs81003 contains a series usb 2.0-compliant high-speed switch between the d pin and d min pins and between the d pout and d mout pins. this switch is designed for high-speed, low-latency functionality to allow usb 2.0 full-speed and high-speed communications with minimal interference. nominally, the switch is closed in the active state, allowing uninterrupted usb communications between the upstream host and the portable device. the switch is opened when: ? the ucs81003 is actively emulating using any of the charger emulation profiles except cdp (by default - see section 10.4.5 ?high-speed switch configuration register? ) ? the ucs81003 is operating as a dedicated charger unless the hsw_dce configuration bit is set (see section 10.4.5 ?high-speed switch configuration register? ) ? the ucs81003 is in the detect state (by default) or in the sleep state 6.1 usb-if high-speed compliance the usb data switch will not significantly degrade the signal integrity through the device d p /d m pins with usb high-speed communications. note: if the v dd voltage is less than v dd_th , the high-speed data switch will be disabled and opened.
? 2014 microchip technology inc. ds20005334a-page 33 ucs81003 7.0 usb port power switch to assure compliance to various charging specifications, the ucs81003 contains a usb port power switch that supports two current-limiting modes: trip and constant current (variable slope). the current limit (i lim ) is pin selectable (and may be updated via the register set). the switch also includes soft start circuitry and a separate short-circuit current limit. the port power switch is on in the active state (except when v bus is discharging). 7.1 current limiting 7.1.1 current limit setting the ucs81003 hardware set current limit (i lim ), can be one of eight values (see table 11-1 ). this resistor value is read once upon ucs81003 power-up. the current limit can be changed via the smbus/i 2 c after power- up; however, the programmed current limit cannot exceed the hardware set current limit. at power-up, the communication mode (stand-alone or smbus/i 2 c) and hardware current limit (i lim ) are determined via the pull-down resistor (or pull-up resistor, if connected to v dd ) on the comm_sel/i lim pin, as shown in table 11-1 . 7.1.2 short circuit output current limiting short circuit current limiting occurs when the output current is above the selectable current limit (i limx ). this event will be detected and the current will immediately be limited (within t short_lim time). if the condition remains, the port power switch will flag an error condition and enter the error state (see section 5.1.5 ?error state operation? ). 7.1.3 soft start when the pwr_en control changes states to enable the port power switch, or an attach detection event occurs in the detect power state and the pwr_en control is already enabled, the ucs81003 invokes a soft start routine for the duration of the v bus rise time (t r_bus ). this soft start routine will limit current flow from v s into v bus while it is active. this circuitry will prevent current spikes due to a step in the portable device current draw. in the case when a portable device is attached while the pwr_en pin is already enabled, if the bus current exceeds i lim , the ucs81003 current limiter will respond within a specified time (t short_lim ) and will operate normally at this point. the c bus capacitor will deliver the extra current, if any, as required by the load change. 7.1.4 current-limiting modes the ucs81003 current limiting has two modes: trip and constant current (variable slope). either mode functions at all times when the port power switch is closed. the current limiting mode used depends on the active state mode (see section 9.9 ?current limit mode associations? ). when operating in the detect power state (see section 5.1.3 ?detect state operation? ), the current capacity at v bus is limited to i bus_byp as described in section 8.2 ?vbus bypass switch? . 7.1.4.1 trip mode when using trip current limiting, the ucs81003 usb port power switch functions as a low-resistance switch and rapidly turns off if the current limit is exceeded. while operating using trip current limiting, the v bus output voltage will be held relatively constant (equal to the v s voltage minus the r on xi bus current) for all current values up to the i lim . if the current drawn by a portable device exceeds i lim , the following occurs: 1. the port power switch will be turned off (trip action). 2. the ucs81003 will enter the error state and assert the alert# pin. 3. the fault handling circuitry will then determine subsequent actions. trip current limiting is used by default when the ucs81003 is in data pass-through and dedicated charger emulation cycle (except when the bc1.2 dcp charger emulation profile is accepted), and when there?s no handshake. this method is also used when charger emulation is active. 7.1.4.2 constant current limiting (variable slope) constant current limiting is used when a portable device handshakes using the bc1.2 dcp charger emulation profile and the current drawn is greater than i lim (and i lim < 1.68a). it is also used in bc1.2 cdp mode and during the dce cycle when a charger emu- lation profile is being applied and the emulation timeout is active. in cc mode, the port power switch allows the attached portable device to reduce v bus output voltage to less than the input v s voltage while maintaining current delivery. the v/i slope depends on the user set i lim value. this slope is held constant for a given i lim value. note: to avoid cycling in trip mode, set i lim higher than the highest expected portable device current draw.
ucs81003 ds20005334a-page 34 ? 2014 microchip technology inc. 7.2 thermal management and voltage protection 7.2.1 thermal management the ucs81003 utilizes two-stage internal thermal management. the first is named dynamic thermal management and the second is a fixed thermal shutdown. 7.2.1.1 dynamic thermal management for the first stage (active in both current limiting modes), referred to as dynamic thermal management, the ucs81003 automatically adjusts port power switch limits and modes to lower power dissipation when the thermal regulation temperature value is approached, as described below. if the internal temperature exceeds the t reg value, the port power switch is opened, the current limit (i lim ) will be lowered by one step and a timer is started (t dc_temp ). when this timer expires, the port power switch is closed and the internal temperature will be checked again. if it remains above the t reg threshold, the ucs81003 will repeat this cycle (open port power switch and reduce the i lim setting by one step) until i lim reaches its minimum value. if the ucs81003 is operating using constant current limiting (variable slope) and the i lim setting has been reduced to its minimum set point and the temperature is still above t reg , the ucs81003 will switch to operating using trip current limiting. this will be done by reducing the i bus_r2min setting to 120 ma and restoring the i lim setting to the value immediately below the programmed setting (e.g., if the programmed i lim is 2.05a, the value will be set to 1.68a). if the temperature continues to remain above t reg , the ucs81003 will continue this cycle (open the port power switch and reduce the i lim setting by one step). if the ucs81003 internal temperature drops below t reg ?t reg_hyst , the ucs81003 will take action based on the following: 1. if the current limit mode changed from cc mode to trip mode, then a timer is started. when this timer expires, the ucs81003 will reset the port power switch operation to its original configuration, allowing it to operate using constant current limiting (variable slope). 2. if the current limit mode did not change from cc mode to trip mode, or was already operating in trip mode, the ucs81003 will reset the port power switch operation to its original configuration. if the ucs81003 is operating using trip current limiting and the i lim setting has been reduced to its minimum set point and the temperature is above t reg , the port power switch will be closed and the current limit will be held at its minimum setting until the temperature drops below t reg ?t reg_hyst . 7.2.1.2 thermal shutdown the second-stage thermal management consists of a hardware implemented thermal shutdown corresponding to the maximum allowable internal die temperature (t tsd ). if the internal temperature exceeds this value, the port power switch will immediately be turned off until the temperature is below t tsd ?t tsd_hyst . 7.3 v bus discharge the ucs81003 will discharge v bus through an internal 100 ? resistor when at least one of the following conditions occurs: ? the pwr_en control is disabled (triggered on the inactive edge of the pwr_en control). ? a portable device removal detection event is flagged. ?the v s voltage drops below a specified threshold (v s_uvlo ) that causes the port power switch to be disabled. ? when commanded into the sleep power state via the em_en, m1 and m2 controls. ? before each charger emulation profile is applied. ? upon recovery from the error state. ? when commanded via the smbus (see section 10.4 ?configuration registers? ) in the active state. ? any time that the port power switch is activated after the v bus bypass switch has been on (i.e., whenever v bus voltage transitions from being driven from v dd to being driven from v s , such as going from detect to active power state). ? any time that the v bus bypass switch is activated after the port power switch has been on (i.e., going from active to detect power state). note 1: if the temperature exceeds the t reg threshold while operating in the dce cycle mode after a charger emulation pro- file has been accepted, the profile will be removed. the ucs81003 will not restart the dce cycle until one of the control inputs changes states to restart emulation. 2: the ucs81003 will not actively discharge v bus as a result of the temperature exceeding t reg ; however, any load current provided by a portable device or other load will cause v bus to be discharged when the port power switch is opened, possibly resulting in an attached portable device resetting.
? 2014 microchip technology inc. ds20005334a-page 35 ucs81003 when the v bus discharge circuitry is activated, at the end of the t discharge time, the ucs81003 will confirm that v bus was discharged. if the v bus voltage is not below the v test level, a discharge error will be flagged (by setting the disch_err status bit) and the ucs81003 will enter the error state. 7.4 battery full delivery of bus current to a portable device can be rationed by the ucs81003. when this functionality is enabled, the host system must provide the ucs81003 with an accumulated charge maximum limit (in mah). the charge rationing functionality works only in the active power state. it continuously monitors the current delivered as well as the time elapsed since the mode was activated (or since the data was updated). this information is compiled to generate a charge-rationing number that is checked against the host limit. once the programmed current-rationing limit has been reached, the ucs81003 will take action as determined by the ration_beh bits, as described in table 7-1 . note that this does not cause the device to enter the error state. once the charge rationing circuitry has reached the programmed threshold, the ucs81003 will maintain the desired behavior until charge rationing is reset. once charge rationing has been reset or disabled, the ucs81003 will recover as shown in ta b l e 7 - 2 . table 7-1: charge rat ioning behavior ration_beh<1:0> behavior actions taken notes 10 00 report alert# pin asserted. 01 report and disconnect (default) 1. alert# pin asserted. 2. charger emulation profile removed. 3. port power switch disconnected. the hsw will not be affected. all bus monitoring is still active. changing the m1, m2, em_en, s0 and pwr_en controls will cause the device to change power states as defined by the pin combinations; however, the port power switch will remain off until the rationing circuitry is reset. furthermore, the bypass switch will not be turned on if enabled via the s0 control. 10 disconnect and go to sleep 1. port power switch disconnected. 2. charger emulation profile removed. 3. device will enter the sleep state. the hsw will be disabled. all vbus and vs monitoring will be stopped. changing the m1, m2, em_en, s0, and pwr_en controls will have no effect on the power state until the rationing circuitry is reset. 11 ignore take no further action. table 7-2: charge rationi ng reset behavior behavior reset actions report 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. release the alert# pin. report and disconnect 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. release the alert# pin. 4. check the m1, m2, em_en, s0 and pwr_en controls and enter the indicated power state if the controls changed ( note 1 ). note 1: any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). if the pin conditions have not changed, the ucs81003 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge v bus or restart emulation).
ucs81003 ds20005334a-page 36 ? 2014 microchip technology inc. 7.4.1 charge rationing interactions when charge rationing is active, regardless of the specified behavior, the ucs81003 will function normally until the charge rationing threshold is reached. note that charge rationing is only active when the ucs81003 is in the active state, and it does not automatically reset when a removal or attach detection event occurs. charger emulation will start over if a removal detection event and attach detection event occur while charge rationing is active and the charge rationing threshold has not been reached. this allows charging of sequential portable devices while charge is being rationed, which means that the accumulated power given to several portable devices will still be held to the stated rationing limit. changing the charge rationing behavior will have no effect on the charge rationing data registers. if the behavior is changed prior to reaching the charge rationing threshold, this change will occur and be transparent to the user. when the charge rationing threshold is reached, the ucs81003 will take action, as shown in tab l e 7 - 1 . if the behavior is changed after the charge rationing threshold has been reached, the ucs81003 will immediately adopt the newly programmed behavior, clearing the alert# pin and restoring switch operation respectively (see tab le 7 - 3 ). disconnect and go to sleep 1. reset the total accumulated charge registers. 2. clear the ration status bit. 3. check the m1, m2, em_en, s0 and pwr_en controls and enter the indicated power state if the controls changed ( note 1 ). ignore 1. reset the total accumulated charge registers. 2. clear the ration status bit. table 7-2: charge rationing reset behavior (continued) behavior reset actions note 1: any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). if the pin conditions have not changed, the ucs81003 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge v bus or restart emulation). table 7-3: effects of changing rationing behavior after threshold reached previous behavior new behavior actions taken ignore report assert alert# pin. report and disconnect 1. assert alert# pin. 2. remove charger emulation profile. 3. open port power switch. see the report and disconnect (default) in ta b l e 7 - 1 . disconnect and go to sleep 1. remove charger emulation profile. 2. open port power switch. 3. enter the sleep state. see the disconnect and go to sleep entry in table 7-1 . note 1: any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). if the pin conditions have not changed, the ucs81003 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge v bus or restart emulation).
? 2014 microchip technology inc. ds20005334a-page 37 ucs81003 if the rtn_en control is set to ? 0 ? prior to reaching the charge rationing threshold, rationing will be disabled and the total accumulated charge registers will be cleared. if the rtn_en control is set to ? 0 ? after the charge rationing threshold has been reached, the following will be done: 1. ration status bit will be cleared. 2. the alert# pin will be released if asserted by the rationing circuitry and no other conditions are present. 3. the m1, m2, em_en, s0 and pwr_en controls are checked to determine the power state. see note 1 in tab l e 7 - 3 . setting the rtn_rst control to ? 1 ? will automatically reset the total accumulated charge registers to 00_00h. if this is done prior to reaching the charge rationing threshold, the data will continue to be accumulated restarting from 00_00h. if this is done after the charge rationing threshold is reached, the ucs81003 will take action, as shown in table 7-2 . report ignore release alert# pin. report and disconnect open port power switch. see the report and disconnect (default) entry in table 7-1 . disconnect and go to sleep 1. release the alert# pin. 2. remove charger emulation profile. 3. open the port power switch. 4. enter the sleep state. see the disconnect and go to sleep entry in ta b l e 7 - 1 . report and disconnect ignore 1. release the alert# pin. 2. check the m1, m2, em_en, s0 and pwr_en controls and enter the indicated power state if the controls changed (see note 1 ). report check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 1 ). disconnect and go to sleep 1. release the alert# pin. 2. enter the sleep state. see the disconnect and go to sleep entry in ta b l e 7 - 1 . disconnect and go to sleep ignore check the m1, m2, em_en, s0, and pwr_en controls and enter the indicated power state if the controls changed (see note 1 ). report 1. assert the alert# pin. 2. check the m1, m2, em_en, s0 and pwr_en controls and enter the indicated power state if the controls changed (see note 1 ). report and disconnect 1. assert the alert# pin. 2. check the m1, m2, em_en, s0 and pwr_en controls to determine the power state, then enter that state except that the port power switch and bypass switch will not be closed (see note 1 ). table 7-3: effects of changing rationing behavior after threshold reached previous behavior new behavior actions taken note 1: any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). if the pin conditions have not changed, the ucs81003 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge v bus or restart emulation). note: if the rationing behavior was set to ?report and disconnect? when the charge rationing threshold was reached, and then the rtn_en bit is cleared, the portable device may start charging sub-optimally because the charger emulation profile has been removed. toggle the pwr_en control to restart charger emulation.
ucs81003 ds20005334a-page 38 ? 2014 microchip technology inc. 7.5 fault handling mechanism the ucs81003 has two modes for handling faults: ? latch (latch-upon-fault) ? auto-recovery (automatically attempt to restore the active power state after a fault occurs). if the smbus is actively utilized, auto-recovery fault handling is the default error handler as determined by the latchs bit (see section 10.4.3 ?switch configuration register? ). otherwise, the fault handling mechanism used depends on the state of the latch pin. faults include overcurrent, overvoltage (on v s ), undervoltage (on v bus ), back-voltage (v bus to v s , or v bus to v dd ), discharge error and maximum allowable internal die temperature (t tsd ) exceeded (see section 5.1.5 ?error state operation? ). 7.5.1 auto-recovery fault handling when the latch control is low, auto-recovery fault handling is used. when an error condition is detected, the ucs81003 will immediately enter the error state and assert the alert# pin (see section 5.1.5 ?error state operation? ). independently from the host controller, the ucs81003 will wait a preset time (t cycle ), check error conditions (t tst ) and restore active operation if the error condition(s) no longer exist. if all other conditions that may cause the alert# pin to be asserted have been removed, the alert# pin will be released. figure 7-1: error recovery timing (short circuit example). 7.5.2 latched fault handling when the latch control is high, latch fault handling is used. when an error condition is detected, the ucs81003 will enter the error power state and assert the alert# pin. upon command from the host controller (by toggling the pwr_en control from enabled to disabled or by clearing the err bit via smbus), the ucs81003 will check error conditions once and restore active operation if error conditions no longer exist. if an error condition still exists, the host controller is required to issue the command again to check error conditions. t rst v bus i bus short applied. i tst t discharge i tst v test short detected. v bus discharged. enter error state. check short condition. short still present. return to error state. wait t cycle . wait t cycle . check short condition. short removed. return to normal operation. t cycle t cycle t rst
? 2014 microchip technology inc. ds20005334a-page 39 ucs81003 8.0 detect state 8.1 device attach/removal detection the ucs81003 can detect the attachment and removal of a portable device on the usb port. attach and removal detection does not perform any charger emulation or qualification of the device. the high-speed switch is ?off? (by default) during the detect power state. 8.2 v bus bypass switch the ucs81003 contains circuitry to provide v bus current as shown in figure 8-1 . in the detect state, v dd is the voltage source; in the active state, v s is the voltage source. the bypass switch and the port power switch are never both on at the same time. while the v bus bypass switch is active, the current available to a portable device will be limited to i bus_byp , and the attach detection feature is active. figure 8-1: detect state v bus biasing. 8.3 attach detection the primary attach detection feature is only active in the detect power state. when active, this feature constantly monitors the current load on the v bus pin. if the current drawn by a portable device is greater than i det_qual for longer than t det_qual , an attach detection event occurs. this will cause the a_det# pin to assert low and the adet_pin and att status bits to be set. until the port power switch is enabled, the current available to a portable device will be limited to that used to detect device attachment (i det_qual ). once an attach detection event occurs, the ucs81003 will wait for the pwr_en control to be enabled (if not already). when pwr_en is enabled and v s is above the threshold, the ucs81003 will activate the usb port power switch and operate in the selected active mode (see section 9.0 ?active state? ). 8.4 removal detection the removal detection feature will be active in the active and detect power states if s0 = ? 1 ?. this feature monitors the current load on the v bus pin. if this load drops to less than i rem_qual_det for longer than t rem_qual , a removal detection event is flagged. when this event occurs, the following will be performed: 1. disable the port power switch and the bypass switch. 2. de-assert the a_det# pin and set the rem status register bit. 3. enable an internal discharging device that will discharge the v bus line within t discharge . 4. once the v bus pin has been discharged, the device will return to the detect state regardless of the pwr_en control state. port power switch v dd v s v s v bus v bus bypass switch v s v bus
ucs81003 ds20005334a-page 40 ? 2014 microchip technology inc. 9.0 active state 9.1 active state overview the ucs81003 has the following modes of operation in the active state: data pass-through, bc1.2 dcp, bc1.2 sdp, bc1.2 cdp and dedicated charger emulation cycle. the current limiting mode depends on the active mode behavior (see tab l e 9 - 2 ). 9.2 active mode selection the active mode selection is controlled by three controls: em_en, m1 and m2, as shown in table 9-1 . 9.3 bc1.2 detection renegotiation the bc1.2 specification allows a charger to act as an sdp, cdp or dcp and to change between these roles. to force an attached portable device to repeat the charging detection procedure, v bus must be cycled. in compliance with this specification, the ucs81003 automatically cycles v bus when switching between the bc1.2 sdp, bc1.2 dcp and bc1.2 cdp modes. 9.4 data pass-through (no charger emulation) when commanded to data pass-through mode, ucs81003 will close its usb high-speed data switch to allow usb communications between a portable device and host controller and will operate using trip current limiting. no charger emulation profiles are applied in this mode. data pass-through mode will persist until commanded otherwise by the m1, m2 and em_en controls. 9.5 bc1.2 sdp (no charger emulation) when commanded to bc1.2 sdp mode, ucs81003 will discharge v bus , close its usb high-speed data switch to allow usb communications between a portable device and host controller, and will operate using trip current limiting. no charger emulation profiles are applied in this mode. bc1.2 sdp mode will persist until commanded otherwise by the m1, m2, em_en and pwr_en controls. 9.6 bc1.2 cdp when bc1.2 cdp is selected as the active mode, ucs81003 will discharge v bus , close its usb high-speed data switch (by default), and apply the bc1.2 cdp charger emulation profile which performs handshaking per the specification. the combination of the ucs81003 cdp handshake along with a standard usb host comprises a charging downstream port. in bc1.2 cdp mode, there is no emulation timeout. if the handshake is successful, the ucs81003 will operate using constant current limiting (variable slope). if the handshake is not successful, the ucs81003 will leave the applied cdp profile in place, leave the high-speed switch closed, enable constant current limiting, and persist in this condition until commanded otherwise by the m1, m2, em_en and pwr_en controls. table 9-1: active mode selection m1 m2 em_en active mode 00 1 dedicated charger emulation cycle 01 0 data pass-through 01 1 bc1.2 dcp 10 0 bc1.2 sdp - note 1 10 1 dedicated charger emulation cycle 11 0 data pass-through 11 1 bc1.2 cdp note 1: bc1.2 sdp behaves the same as the data pass-through mode with the exception that it is preceded by a v bus discharge when the mode is entered per the bc1.2 specification. note 1: if it is desired that the data pass-through mode operates as a traditional/standard port power switch, the s0 control should be set to ? 0 ? to allow the port power switch to be closed without requiring an attach detection event. when entering this mode, there is no automatic v bus discharge. 2: when the m1, m2 and em_en controls are set to ? 0 ?, ? 1 ?, ? 0 ? or to ? 1 ?, ? 1 ?, ? 0 ? respectively, data pass-through mode will persist if the pwr_en control is disabled; however, the ucs81003 will draw more current. to leave the data pass-through mode, the pwr_en control must be enabled before the m1, m2 and em_en controls are changed to the desired mode. note: if it is desired that the bc1.2 sdp mode operates as a traditional/standard port power switch, the s0 control should be set to ? 0 ? to allow the port power switch to be closed without requiring an attach detection event.
? 2014 microchip technology inc. ds20005334a-page 41 ucs81003 the ucs81003 will respond per the bc1.2 specification to the portable device initiated charger renegotiation requests. 9.6.1 bc1.2 cdp charger emulation profile the bc1.2 cdp charger emulation profile acts in a reactionary manner based on stimulus from the portable device as described below and shown in figure 2-1 . 1. v bus voltage is applied. 2. primary detection - when the portable device drives a voltage between 0.4v and 0.8v onto the d pout pin, the ucs81003 will drive 0.6v onto the d mout pin within 20 ms. 3. when the portable device drives the d pout pin back to ? 0 ?, the ucs81003 will then drive the d mout pin back to ? 0 ? within 20 ms. 4. optional secondary detection - if the portable device then drives a voltage of 0.6v (nominal) onto the d mout pin, the ucs81003 will take no other action. this will cause the portable device to observe a ? 0 ? on the d pout pin and know that it is connected to a cdp. 9.7 bc1.2 dcp when bc1.2 dcp is selected as the active mode, ucs81003 will discharge v bus and apply the bc1.2 dcp charger emulation profile per the specification. in bc1.2 dcp mode, the emulation timeout and requirement for portable device current draw are automatically disabled. when the bc1.2 dcp charger emulation profile is applied within the dedicated charger emulation cycle (see section 9.11.3 ?legacy 3 charger emulation profile? ), the timeout and current draw requirement are enabled. if the portable device is charging after the dcp charger emulation profile is applied, the ucs81003 will leave in place the resistive short, leave the high- speed switch open and enable constant current limiting (variable slope). 9.7.1 bc1.2 dcp charger emulation profile the bc1.2 dcp charger emulation profile is described as follows: 1. v bus voltage is applied. a resistor (r dcp_res ) is connected between the d pout and d mout pins. 2. primary detection - if the portable device drives 0.6v (nominal) onto the d pout pin, the ucs81003 will take no other action than to leave the resistor connected between d pout and d mout . this will cause the portable device to see 0.6v (nominal) on the d mout pin and know that it is connected to a dcp. 3. optional secondary detection - if the portable device drives 0.6v (nominal) onto the d mout pin, the ucs81003 will take no other action than to leave the resistor connected between d pout and d mout . this will cause the portable device to see 0.6v (nominal) on the d pout pin and know that it is connected to a dcp. 9.8 dedicated charger when commanded to dedicated charger emulation cycle mode, the ucs81003 enables an attached portable device to enter its charging mode by applying specific charger emulation profiles in a predefined sequence. using these profiles, the ucs81003 is capable of generating and recognizing several signal levels on the d pout and d mout pins. the preloaded charger emulation profiles include ones compatible with yd/t-1591 (2009), 12w charging, samsung and many rim portable devices. other levels, sequences and protocols are configurable via the smbus/i 2 c. when a charger emulation profile is applied, a programmable timer for the emulation profile is started. when emulation timeout occurs, the ucs81003 checks the i bus current against a programmable threshold. if the current is above the threshold, the charger emulation profile is accepted and the associated current limiting mode is applied. no active usb data communication is possible when charging in this mode (by default - see section 10.4.5 ?high- speed switch configuration register? ). note 1: bc1.2 compliance testing may require the s0 control to be set to ? 0 ? (attach and removal detection feature disabled) while testing is in progress. 2: when the ucs81003 is in bc1.2 cdp mode and the attach and removal detection feature is enabled, if a power thief (such as a usb light or fan) attaches but does not assert d p pin, a removal event will not occur when the portable device is removed. however, if a standard usb device is subsequently attached, removal detection will again be fully functional. as well, if pwr_en is cycled or m1, m2 and/or em_en change state, a removal event will occur and attach detection will be reactivated. note: all cdp handshaking is performed with the high-speed switch closed. note: bc1.2 compliance testing may require the s0 control to be set to ? 0 ? (attach and removal detection feature disabled) while testing is in progress.
ucs81003 ds20005334a-page 42 ? 2014 microchip technology inc. 9.8.1 emulation reset prior to applying any of the charger emulation profiles, the ucs81003 will perform an emulation reset. this means that the ucs81003 resets the v bus line by disconnecting the port power switch and connecting v bus to ground via an internal 100 ? resistor for t discharge time. the port power switch will be held open for a time equal to t em_reset at which point the port power switch will be closed and the v bus voltage applied. the d pout and d mout pins will be pulled low using internal 15 k ? pull-down resistors. 9.8.2 emulation cycling in dedicated charger emulation cycle mode, the charger emulation profiles (if enabled) will be applied in the following order: 1. legacy 1 2. legacy 2 3. legacy 3 4. legacy 4 5. legacy 5 6. legacy 6 7. legacy 7 8. custom (disabled by default). if the cs_frst configuration bit is set, then the custom charger emulation profile will be tested first and the order will proceed as given. if s0 = ? 0 ? and a portable device is not attached in dce cycle mode, the ucs81003 will be cycling through charger emulation profiles (by default). there is no guarantee which charger emulation profile will be applied first when a portable device attaches. the ucs81003 will apply a charger emulation profile until one of the following exit conditions occurs: ? current greater than i bus_chg is detected flowing out of v bus at the respective emulation timeout time. in this case, the profile is assumed to be accepted and no other profiles will be applied. ? the respective emulation timeout (t em_timeout ) time is reached without current that exceeds the i bus_chg limit flowing out of v bus (the emulation timeout is enabled by default, see section 10.4.2 ?emulation configuration register? and register 10-35 ). the profile is assumed to be rejected, and the ucs81003 will perform emulation reset and apply the next profile, if there is one. emulation timeouts can be programmed for each charger emulation profile (see section 10.11 ?preloaded emulation timeout configuration registers? and register 10-35 ). 9.8.3 dce cycle retry if none of the charger emulation profiles cause a charge current to be drawn, the ucs81003 will perform emulation reset and cycle through the profiles again (if the em_retry bit is set (default - see section 10.4.2 ?emulation configuration register? ). the ucs81003 will continue to cycle through the profiles as long as charging current is not drawn and the pwr_en control is enabled. if the emulation retry is not enabled, the ucs81003 will flag ?no handshake? and end the dce cycle using trip current limiting. 9.9 current limit mode associations the ucs81003 will close the port power switch and use the current limiting mode as shown in tab l e 9 - 2 . note: to help prevent possible damage to a portable device, the d pout and d mout pins have current limiting in place when the emulation profiles are applied. table 9-2: current limit mode options active mode current limit mode (see section 10.14 ?current limiting behavior configuration registers? ) data pass-through trip mode bc1.2 sdp trip mode bc1.2 cdp cc mode if i lim < 1.68a, otherwise, trip mode bc1.2 dcp cc mode if i lim < 1.68a, otherwise, trip mode dce cycle during dce cycle when a charger emulation profile is being applied and the emulation timeout is active cc mode if i lim < 1.68a, otherwise, trip mode note 1: as noted in the last three rows in tab l e 9 - 2 , under those specific conditions with i lim < 1.68a, it is the relationship of i lim and i bus_r2min that determines the current limiting mode. in these cases, the value of i bus_r2min is determined by cs_r2_imin<2:0> bits 4-2 in the custom current limiting behavior configuration register - 51h ( register 10-49 ).
? 2014 microchip technology inc. ds20005334a-page 43 ucs81003 9.10 no handshake in dce cycle mode with emulation retry disabled, a no handshake condition is flagged (the no_hs status bit stays set (see register 10-5 ) when the end of the dce cycle is reached without a handshake and without drawing current. all signatures/handshaking placed on the d pout and d mout pins are removed. the ucs81003 will operate with the high-speed switch opened or closed as determined by the high-speed switch configuration, and will use trip or constant current limiting, as determined by the i bus_r2min setting (cs_r2_imin<2:0> bits 4-2 in the custom current limiting behavior configuration register 51h). the portable devices that can cause this are generally the ones that pull up d pout to some voltage and leave it there, or apply the wrong voltage. 9.11 preloaded charger emulation profiles the following charger emulation profiles are resident to the ucs81003: ? legacy 1 charger emulation profile ? legacy 2, 4, 5 and 7 charger emulation profiles ? legacy 3 charger emulation profile ? legacy 6 charger emulation profile ? bc1.2 cdp charger emulation profile ? bc1.2 dcp charger emulation profile 9.11.1 legacy 1 charger emulation profile legacy 1 charger emulation profile does the following: 1. the ucs81003 will apply 900 mv to both the d pout and the d mout pins. 2. v bus voltage is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs81003 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device. charging commences. the voltages applied to the d pout and d mout pins will remain in place (unless em_resp is set to 0b ). the ucs81003 will begin operating in trip mode or cc mode as determined by the i bus_r2min setting (see section 10.14 ?current limiting behavior configuration registers? ). 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs81003 will stop the currently applied charger emulation profile. this will cause all voltages put onto the d pout and d mout pins to be removed. emulation reset occurs, and the ucs81003 will initiate the next charger emulation profile. 9.11.2 legacy 2, 4, 5 and 7 charger emulation profiles legacy 2, 4, 5 and 7 charger emulation profiles follow the same pattern of operation, although the voltage that is applied on the d pout and d mout pins will vary. they do the following: 1. the ucs81003 will apply a voltage on the d pout pin using either a current-limited voltage source or a voltage divider between v bus and ground with the center tap on the d pout pin. 2. the ucs81003 will apply a possibly different voltage on the d mout pin, using either a current- limited voltage source or a voltage divider between v bus and ground, with the center tap on the d mout pin. 3. v bus voltage is applied. legacy 3 charger emulation profile accepted or the emulation timeout is disabled cc mode if i lim < 1.68a, otherwise, trip mode legacy 1, legacy 2 or legacy 4 - legacy 7 charger emulation profile accepted or the emulation timeout is disabled trip mode if i bus_r2min 1.68a (normal operation), otherwise, cc mode (see register 10-49 ) custom charger emulation profile accepted or the emulation timeout is disabled trip mode if i bus_r2min 1.68a (normal operation), otherwise, cc mode (see register 10-49 ) no handshake (dce cycle with emulation retry not enabled) trip mode if ibus_r2min 1.68a (normal operation), otherwise, cc mode (see register 10-49 ) table 9-2: current limit mode options (continued) active mode current limit mode (see section 10.14 ?current limiting behavior configuration registers? ) note 1: as noted in the last three rows in tab l e 9 - 2 , under those specific conditions with i lim < 1.68a, it is the relationship of i lim and i bus_r2min that determines the current limiting mode. in these cases, the value of i bus_r2min is determined by cs_r2_imin<2:0> bits 4-2 in the custom current limiting behavior configuration register - 51h ( register 10-49 ).
ucs81003 ds20005334a-page 44 ? 2014 microchip technology inc. 4. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs81003 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device. charging commences. the voltages applied to the d pout and d mout pins will remain in place (unless em_resp is set to 0b ). the ucs81003 will begin operating in trip mode or cc mode, as determined by the i bus_r2min setting (see section 10.14 ?current limiting behavior configuration registers? ). 5. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs81003 will stop the currently applied charger emulation profile. this will cause all voltages put onto the d pout and d mout pins to be removed. emulation reset occurs, and the ucs81003 will initiate the next charger emulation profile. additionally, the user may ?build? a charger emulation profile by determining the voltage and resistance characteristics that are placed on each of the d pout and d mout pins. see section 9.12 ?custom charger emulation profile? . 9.11.3 legacy 3 charger emulation profile the legacy 3 charger emulation profile does the following: 1. the ucs81003 will connect a resistor (r dcp_res ) between d pout and d mout . 2. v bus is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires (enabled by default), the ucs81003 will accept that this is the correct charger emulation profile for the attached portable device. charging commences. the resistive short between the d pout and d mout pins will be left in place. 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs81003 will stop the legacy 3 charger emulation. this will cause resistive short between the d pout and d mout pins to be removed. emulation reset occurs, and the ucs81003 will initiate the next charger emulation profile. 9.11.4 legacy 6 charger emulation profile the legacy 6 charger emulation profile does the following: 1. the ucs81003 will apply a voltage on the d pout pin using a voltage divider between v bus and ground with the center tap on the d pout pin. 2. v bus voltage is applied. 3. if the portable device draws more than i bus_chg current when the t em_timeout timer expires, the ucs81003 will accept that legacy 6 is the correct charger emulation profile for the attached portable device. charging commences. the voltage applied to the d pout pin will remain in place (unless em_resp is set to 0b ). the ucs81003 will begin operating in trip mode or cc mode, as determined by the i bus_r2min setting (see section 10.14 ?current limiting behavior configuration registers? ). 4. if the portable device does not draw more than i bus_chg current when t em_timeout timer expires, the ucs81003 will stop the legacy 6 charger emulation profile. this will cause the voltage put onto the d pout pin to be removed. emulation reset occurs, and the ucs81003 will initiate the next charger emulation profile. 9.12 custom charger emulation profile the ucs81003 allows the user to create a custom charger emulation profile to handshake as any type of charger. this profile can be included in the dce cycle. in addition, it can be placed first or last in the profile sequence in the dce cycle. see register 10-35 . the custom charger emulation profile uses a number of registers to define stimuli and behaviors. the custom charger emulation profile uses three separate stimulus/response pairs that will be detected and applied in sequence, allowing flexibility to ?build? any of the preloaded emulation profiles, or tailor the profile to match a specific charger application. for details, see application note 24.14 ? ?ucs1002 fundamentals of custom charger emulation? .
? 2014 microchip technology inc. ds20005334a-page 45 ucs81003 10.0 register description the registers shown in table 10-1 are accessible through the smbus or i 2 c. while in the sleep state, the ucs81003 will retain configuration and charge rationing data as indicated in the text. if a register does not indicate that data will be retained in the sleep power state, this information will be lost when the ucs81003 enters the sleep power state. table 10-1: register set in hexadecimal order register address register name r/w function default value page no. 00h current measurement r stores the current measurement 00h 47 01h total accumulated charge high byte r stores the total accumulated charge delivered high byte 00h 48 02h total accumulated charge middle high byte r stores the total accumulated charge delivered middle high byte 00h 48 03h total accumulated charge middle low byte r stores the total accumulated charge delivered middle low byte 00h 48 04h total accumulated charge low byte r stores the total accumulated charge delivered low byte 00h 48 0fh other status r indicates emulation status as well as the alert# and a_det# pin status 00h 49 10h interrupt status see register 10-3 indicates why alert# pin asserted 00h 50 11h general status r/r-c indicates general status 00h 51 12h profile status 1 r indicates which charger emulation pro- file was accepted 00h 52 13h profile status 2 r 00h 53 14h pin status r indicates the pin states of the internal control pins 00h 54 15h general configuration r/w controls basic functionality 01h 55 16h emulation configuration r/w controls emulation functionality 8ch 56 17h switch configuration r/w controls advanced switch functions 04h 57 18h attach detect configuration r/w controls attach detect functionality 46h 58 19h current limit r/w controls the maximum current limit 00h 60 1ah charge rationing threshold high byte r/w controls the current threshold i thresh used by the charge rationing circuitry ffh 60 1bh charge rationing threshold low byte r/w controls the current threshold i thresh used by the charge rationing circuitry ffh 60 1ch auto-recovery configuration r/w controls the auto-recovery functionality 2ah 61 1eh i bus_chg configuration r/w stores the limit for i bus_chg used to determine if emulation is successful 0fh 62 1fh t det_charge configuration r/w stores bits that define the t det_charge time 03h 63 20h bcs emulation enable r/w enables bcs charger emulation profiles 16h 63 21h legacy emulation enable r/w enables legacy charger emulation profiles 00h 64 22h bcs emulation timeout config r/w controls timeout for each bcs charger emulation profile 10h 65
ucs81003 ds20005334a-page 46 ? 2014 microchip technology inc. 23h legacy emulation timeout config 1 r/w controls timeout for legacy charger emulation profiles 1 ? 4 6ch 65 24h legacy emulation timeout config 2 r/w controls timeout for legacy charger emulation profiles 5 ? 7 01h 66 25h high-speed switch configuration r/w controls when the high-speed switch is enabled 14h 59 30h applied charger emulation r indicates which charger emulation profile is being applied 00h 67 31h preloaded emulation stimulus 1 - config 1 r indicates the stimulus and timing for stimulus 1 00h 67 32h preloaded emulation stimulus 1 - config 2 r indicates the response and magnitude for stimulus 1 26h 68 33h preloaded emulation stimulus 1 - config 3 r indicates the threshold and pull-up/pull-down settings for stimulus 1 00h 69 34h preloaded emulation stimulus 1 - config 4 r indicates the resistor ratio for stimulus 1 02h 70 35h preloaded emulation stimulus 2 - config 1 r indicates the stimulus and timing for stimulus 2 00h 71 36h preloaded emulation stimulus 2 - config 2 r indicates the response and magnitude for stimulus 2 09h 72 37h preloaded emulation stimulus 2 - config 3 r indicates the threshold and pull- up/pull-down settings for stimulus 2 00h 73 38h preloaded emulation stimulus 2 - config 4 r indicates the resistor ratio for stimulus 2 04h 74 39h preloaded emulation stimulus 3 - config 1 r indicates the stimulus and timing for stimulus 3 ( cdp only ) 00h 75 3ah preloaded emulation stimulus 3 - config 2 r indicates the response and magnitude for stimulus 3 ( cdp only ) 00h 76 3bh preloaded emulation stimulus 3 - config 3 r indicates the threshold and pull- up/pull-down settings for stimulus 3 ( cdp only ) 00h 77 40h custom emulation config r/w controls general configuration of the custom charger emulation profile 01h 79 41h custom stimulus/response pair 1 - config 1 r/w sets the stimulus and timing for stimulus 1 00h 80 42h custom stimulus/response pair 1 - config 2 r/w sets the response and magnitude for stimulus 1 00h 81 43h custom stimulus/response pair 1 - config 3 r/w sets the threshold and pull-up/pull-down settings for stimulus 1 00h 82 44h custom stimulus/response pair 1 - config 4 r/w sets the resistor ratio for stimulus 1 00h 83 45h custom stimulus/response pair 2 - config 1 r/w sets the stimulus and timing for stimulus 2 00h 84 46h custom stimulus/response pair 2 - config 2 r/w sets the response and magnitude for stimulus 2 00h 85 47h custom stimulus/response pair 2 - config 3 r/w sets the threshold and pull-up/pull-down settings for stimulus 2 00h 86 48h custom stimulus/response pair 2 - config 4 r/w sets the resistor ratio for stimulus 2 00h 87 table 10-1: register set in hexadecimal order (continued) register address register name r/w function default value page no.
? 2014 microchip technology inc. ds20005334a-page 47 ucs81003 during power-on reset (por), the default values are stored in the registers. a por is initiated when power is first applied to the part and the voltage on the v dd supply surpasses the v dd_th level, as specified in the electrical characteristics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. when a bit is ?set?, this means that the user writes a logic ? 1 ? to it. when a bit is ?cleared?, this means that the user writes a logic ? 0 ? to it. 10.1 current measurement register (address 00h) the current measurement register stores the measured current value delivered to the portable device (i bus ). this value is updated continuously while the device is in the active power state. the bit weights are in ma and the range is from 0 ma to 2988.6a (the maximum value corresponds to 255 lsb, where 1lsb=11.72ma). this data will be cleared when the device enters the sleep or detect states. this data will also be cleared whenever the port power switch is turned off (including during emulation or any time that v bus is discharged). 10.2 total accumulated charge registers the total accumulated charge registers store the total accumulated charge delivered from the v s source to a portable device. the bit weighting of the registers is given in mah. the register value is reset to 00_00h only when the rtn_rst bit is set or if the rtn_en bit is cleared. this value will be retained when the device transitions out of the active state and resumes accumulation if the device returns to the active state and charge rationing is still enabled. these registers are updated every one (1) second while the ucs81003 is in the active power state. every time the value is updated, it is compared against the target value in the charge rationing threshold registers (see section 10.6 ?charge rationing threshold registers? ). 49h custom emulation stimulus 3 - config 1 r/w sets the stimulus and timing for stimulus 3 00h 88 4ah custom stimulus/response pair 3 - config 2 r/w sets the response and magnitude for stimulus 3 00h 89 4bh custom stimulus/response pair 3 - config 3 r/w sets the threshold and pull-up/pull-down settings for stimulus 3 00h 90 4ch custom stimulus/response pair 3 - config 4 r/w sets the resistor ratio for stimulus 3 00h 91 50h applied current limiting behavior r indicates the applied current limiting behavior 82h 92 51h custom current limiting behavior config r/w controls the custom current limiting behavior 82h 93 fdh product id r stores a fixed value that identifies each product 4eh 94 feh manufacturer id r stores a fixed value that identifies microchip 5dh 94 ffh revision r stores a fixed value that represents the revision number 82h 94 table 10-1: register set in hexadecimal order (continued) register address register name r/w function default value page no. name bits address cof default current measurement 8 00h r 00h name bits address cof default total accumulated charge high byte 8 01h r 00h total accumulated charge middle high 8 02h r 00h total accumulated charge middle low byte 8 03h r 00h total accumulated charge low byte 8 04h r 00h
ucs81003 ds20005334a-page 48 ? 2014 microchip technology inc. 10.3 status registers the status registers store bits that indicate error conditions as well as attach detection and removal detection. unless otherwise noted, these bits will operate as described when the ucs81003 is operating in stand-alone mode. register 10-1: total accumulated charge register (addresses 01h ? 04h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 acc<25> acc<24> acc<23> acc<22 > acc<21> acc<20> acc<19> acc<18> bit 31 bit 24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 acc<17> acc<16> acc<15> acc<14 > acc<13> acc<12> acc<11> acc<10> bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 acc<9> acc<8> acc<7> acc<6> acc<5> acc<4> acc<3> acc<2> bit 15 bit 8 r-0 r-0 r-x r-x r-x r-x r-x r-x acc<1> acc<0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-6 acc<25:0>: total accumulated charge 1 lsb = 0.00325 mah bit 5-0 unimplemented name bits address cof default other status 8 0fh r 00h interrupt status 8 10h r/w 00h general status 8 11h r/r-c 00h profile status 1 8 12h r 00h profile status 2 8 13h r 00h pin status 8 14h r 00h
? 2014 microchip technology inc. ds20005334a-page 49 ucs81003 register 10-2: other status register (address 0fh) u-x u-x r-0 r-0 r-0 r-0 r-0 r-0 ? ? alert_pin adet_pin chg_act em_act em_step<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5 alert_pin: reflects the status of the alert# pin. this bit is set and cleared as the alert# pin changes states. 1 = alert# pin is asserted low 0 = alert# pin is released bit 4 adet_pin: reflects the status of the a_det# pin. when set, indicates that the a_det# pin is asserted low. this bit is set and cleared as the a_det# pin changes states. ( note 1 ) 1 = a_det# pin is asserted low 0 = a_det# pin is released bit 3 chg_act: this bit is automatically set when ibus > i bus_chg and cleared when ibus i bus_chg 0 =ibus (see section 10.12.1 ?applied charger emulation register? ). this bit is set and cleared automatically. ( note 3 ) 1 = device is in active state and emulating 0 = device is not emulating bit 1-0 em_step<1:0>: indicates which stimulus / response pair is currently being applied by the charger emu- lation profile as shown below. these bits are set and cleared automatically. note that the legacy charger emulation profiles and the bc1.2 dcp charger emulation profile do not use stimulus / response pair #3. 00 = none applied. waiting for current. 01 = stimulus/response #1 10 = stimulus/response #2 00 = stimulus/response #3 if applicable note 1: if s0 is ' 1 ', pwr_en is enabled, and v s is not present, the adet_pin bit will cycle if the current draw exceeds the current capacity of the bypass switch. 2: the chg_act bit does not indicate that a portable device has accepted one of the charger emulation pro- files. this bit will cycle during the dedicated charger emulation cycle. 3: the em_act bit does not indicate that a portable device has accepted one of the emulation profiles. this bit will cycle during the dedicated charger emulation cycle.
ucs81003 ds20005334a-page 50 ? 2014 microchip technology inc. register 10-3: interrupt status register (address 10h) r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 err disch_err reset keep_out tsd ov_volt back_v ov_lim bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 err: indicates that an error was detected and the device has entered the error state. writing this bit to a ? 0 ? will clear the error state and allows the device to be returned to the active state. when written to ? 0 ?, all error conditions are checked. if all error conditions have been removed, the ucs81003 returns to the active state. this bit is set automatically by the ucs81003 when the error state is entered. regard- less of the fault handling mechanism used, if any other bit is set in the interrupt status register (10h), the device will not leave the error state. ( note 1 and note 2 ) this bit is cleared automatically by the ucs81003 if the auto-recovery fault handling functionality is active and no error conditions are detected. likewise, this bit is cleared when the pwr_en control is disabled. 1 = one or more errors have been detected, and the ucs81003 has entered the error state. 0 = there are no errors detected. bit 6 disch_err: indicates that the ucs81003 was unable to discharge the v bus node. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 = ucs81003 was unable to discharge the v bus node. 0 =no v bus discharge error. bit 5 reset: indicates that the ucs81003 has just been reset and should be re-programmed. this bit will be set at power up. this bit is cleared when read or when the pwr_en control is toggled. the alert# pin is not asserted when this bit is set. this data is retained in the sleep state. 1 = ucs81003 has just been reset 0 = reset did not occur. bit 4 keep_out: indicates that the v-i output on the v bus pins has dropped below v bus_min. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 =v bus < v bus_min 0 =v bus > v bus_min bit 3 tsd: indicates that the internal temperature has exceeded t tsd threshold and the device has entered the error state. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 = internal temperature > t tsd 0 = internal temperature < t tsd bit 2 ov_volt: indicates that the v s voltage has exceeded the v s_ov threshold and the device has entered the error state. this bit will be cleared when read, if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 =v s > v s_ov 0 =v s < v s_ov bit 1 back_v: indicates that the v bus voltage has exceeded the v s or v dd voltages by more than 150 mv. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 =v bus >v s , or v bus >v dd by more than 150 mv 0 =v bus voltage has not exceeded the v s and v dd voltages by more than 150 mv
? 2014 microchip technology inc. ds20005334a-page 51 ucs81003 bit 0 ov_lim: indicates that the i bus current has exceeded both the i lim threshold and the i bus_r2min thresh- old settings. this bit will be cleared when read if the error condition has been removed or if the err bit is cleared. this bit will cause the alert# pin to be asserted and the device to enter the error state. 1 =i bus > i lim and i bus_r2min 0 =i bus has not exceeded both i lim threshold and the i bus_r2min threshold settings note 1: if the auto-recovery fault handling is not used, the err bit must be written to a logic ' 0 ' to be cleared. it will also be cleared when the pwr_en control is disabled. 2: note that the err bit does not necessarily reflect the alert# pin status. the alert# pin may be cleared or asserted without the err bit changing states. register 10-4: general status register (address 11h) r-0 u-x u-x r-0 r-0 r-c r-c r-c ration ? ? cc_mode treg low_cur rem att bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown c = clear on read bit 7 ration: indicates that the ucs81003 has delivered the programmed amount of power to a portable device. if the ration_beh bits are set to interrupt the host, this bit will cause the alert# pin to be asserted. this bit is cleared when read. this bit is also cleared automatically when the rtn_rst bit is set or the rtn_en bit is cleared (see section 10.4.1 ?general configuration register? ). 1 = ucs81003 has delivered the programmed amount of power to a portable device 0 = ucs81003 has not delivered the programmed amount of power to a portable device bit 6-5 unimplemented bit 4 cc_mode: indicates that the i bus current has exceeded i lim . current is in region 2 (i bus_r2min ). 1 =i bus > i lim 0 =i bus < i lim bit 3 treg: indicates that the internal temperature has exceeded t reg and that the current limit has been reduced. this bit is cleared when read and will not cause the alert# pin to be asserted, unless the alert_link bit is set. 1 = internal temperature > t reg 0 = internal temperature < t reg bit 2 low_cur: indicates that a portable device has reduced its charge current to below ~6.4 ma and may be finished charging. this bit is cleared when read and will not cause the alert# pin to be asserted, unless the alert_link bit is set. 1 =i bus < 6.4 ma 0 =i bus > 6.4 ma bit 1 rem: indicates that a removal detection event has occurred and there is no longer a portable device present. this bit is cleared when read and will not cause the alert# pin to be asserted. it will cause the a_det# pin to be released. 1 = removal detected 0 = no removal detected bit 0 att: indicates that an attach detection event has occurred and there is a new portable device present. this bit is cleared when read and will not cause the alert# pin to be asserted. it will cause the a_det# pin to be asserted. 1 = attach detected 0 = no attach detected register 10-3: interrupt status re gister (address 10h) (continued)
ucs81003 ds20005334a-page 52 ? 2014 microchip technology inc. 10.3.1 profile status 1 register these bits are indicators only and will not cause the alert# pin or a_det# pin to change states. the cust, dcp, cdp and pt bits are cleared under the following circumstances: ? the pwr_en control is disabled ? a new active mode is selected ? a removal detection event occurs. register 10-5: profile status 1 register (address 12h) r-0 u-x u-x r-0 r-0 r-0 r-0 r-0 no_hs ? ? vs_low cust dcp cdp pt bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 no_hs: the no_hs bit is only set during the dedicated charger emulation cycle (see section 9.10 ?no handshake? ). this bit is automatically cleared whenever a new charger emulation profile is applied. ( note 1 ) 1 = no handshake at the end of the dce cycle. 0 = a new charger emulation profile has been applied bit 6-5 unimplemented bit 4 vs_low: indicates that the v s voltage is below the v s_uvlo threshold and the port power switch is held off. this bit is cleared automatically when the v s voltage is above the v s_uvlo threshold. 1 =v s < v s_uvlo 0 =v s > v s_uvlo bit 3 cust: indicates that the portable device successfully performed a handshake with the user-defined custom charger emulation profile during the dce cycle and is charging. based on the custom charger emulation profile configuration, the high-speed switch will be either open or closed (see section 10.13 ?custom emulation configuration registers? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current limiting behavior configuration register? ). 1 = custom profile handshake complete 0 = no custom profile handshake bit 2 dcp: indicates that the portable device accepted the bc1.2 dcp charger emulation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high- speed switch configuration register? ), and the port power switch will use constant current limiting. 1 = dcp handshake complete 0 = no dcp handshake bit 1 cdp: indicates that the portable device successfully performed a handshake with the bc1.2 cdp charger emulation profile and is charging. the high-speed switch will be closed, and the port power switch will use trip current limiting. 1 = cdp handshake complete 0 = no cdp handshake bit 0 pt: indicates that the ucs81003 is in the data pass-through or bc1.2 sdp active mode. the high-speed switch will be closed, and the port power switch will use trip current limiting. ( note 2 ) 1 = ucs81003 is in the data pass-through or bc1.2 sdp active mode. 0 = ucs81003 is not in the data pass-through or bc1.2 sdp active mode. note 1: the no_hs bit does not indicate that a portable device is drawing current and it may be cleared to ? 0 ? (indicating a handshake) and a portable device not charge. this bit is set at the end of each charger emu- lation profile if a portable device does not handshake with it. this bit will not be set at the same time that any other profile status register bits are set. 2: when the ucs81003 is configured as a data pass-through and a removal event and then an attach event occur without changing the active mode, the pt bit will not be set again even though the ucs81003 is still operating as a data pass-through as configured. toggling the m1 control will re-enable the pt status bit.
? 2014 microchip technology inc. ds20005334a-page 53 ucs81003 10.3.2 profile status 2 register these bits indicate which profile was accepted. these bits are indicators only and will not cause the alert# pin or a_det# pin to change states. these bits are cleared under the following circumstances: ? the pwr_en control is disabled ? a new active mode is selected ? a removal detection event occurs. register 10-6: profile status 2 register (address 13h) u-x r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? lg7 lg6 lg5 lg4 lg3 lg2 lg1 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 lg7: indicates that the portable device successfully performed a handshake with the legacy 7 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 7 charger emulation profile and charging. 0 = not charging with legacy 7 charger emulation profile. bit 5 lg6: indicates that the portable device successfully performed a handshake with the legacy 6 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 6 charger emulation profile and charging. 0 = not charging with legacy 6 charger emulation profile. bit 4 lg5: indicates that the portable device successfully performed a handshake with the legacy 5 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 5 charger emulation profile and charging. 0 = not charging with legacy 5 charger emulation profile. bit 3 lg4: indicates that the portable device successfully performed a handshake with the legacy 4 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 4 charger emulation profile and charging. 0 = not charging with legacy 4 charger emulation profile. bit 2 lg3: indicates that the portable device successfully performed a handshake with the legacy 3 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 3 charger emulation profile and charging. 0 = not charging with legacy 3 charger emulation profile.
ucs81003 ds20005334a-page 54 ? 2014 microchip technology inc. 10.3.3 pin status register the pin status register reflects the current pin state of the external control pins as well as identifying the power state. these bits are linked to the x_set bits (see section 10.4.3 ?switch configuration register? ). bit 1 lg2: indicates that the portable device successfully performed a handshake with the legacy 2 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 2 charger emulation profile and charging. 0 = not charging with legacy 2 charger emulation profile. bit 0 lg1: indicates that the portable device successfully performed a handshake with the legacy 1 charger emu- lation profile and is charging. the high-speed switch will be controlled via the hsw_dce bit (see section 10.4.5 ?high-speed switch configuration register? ). the port power switch current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current lim- iting behavior configuration register? ). 1 = handshake successful with the legacy 1 charger emulation profile and charging. 0 = not charging with legacy 1 charger emulation profile. register 10-6: profile status 2 re gister (address 13h) (continued) register 10-7: pin status register (address 14h) u-x r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? pwr_en_pin m2_pin m1_pin em_en_pin sel_pin pwr_state<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 pwr_en_pin: reflects the pwr_en control state. this bit is set and cleared automatically as the pwr_en pin/pwr_ens bit state changes. 1 = pwr_en is logic 1 0 = pwr_en is logic 0 bit 5 m2_pin: reflects the m2 pin state. this bit is set and cleared automatically as the m2 pin/m2_set state changes. 1 = m2 is logic 1 0 = m2 is logic 0 bit 4 m1_pin: reflects the m1 pin state. this bit is set and cleared automatically as the m1 pin/m1_set state changes. 1 = m1 is logic 1 0 = m1 is logic 0 bit 3 em_en_pin: reflects the em_en pin state. this bit is set and cleared automatically as the em_en pin/em_en_set state changes. 1 = em_en is logic 1 0 = em_en logic 0 bit 2 sel_pin: reflects the polarity settings determined by the sel pin decode. this bit is set or cleared auto- matically upon device power-up as the sel pin is decoded. 1 = the pwr_en control is active high 0 = the pwr_en control is active low
? 2014 microchip technology inc. ds20005334a-page 55 ucs81003 10.4 configuration registers the configuration registers control basic device functionality. 10.4.1 general configuration register the contents of this register are retained in sleep. bit 1-0 pwr_state<1:0>: indicates the current power state. these bits are set and cleared automatically as the power state changes. ( note 1 ) 00 =sleep 01 =detect 10 =active 11 = error note 1: accessing the smbus/i 2 c causes the ucs81003 to leave the sleep state. as a result, the pwr_state<1:0> bits will never read as 00b . register 10-7: pin status register (address 14h) (continued) name bits address cof default general configuration 8 15h r/w 01h emulation configuration 8 16h r/w 8ch switch configuration 8 17h r/w 04h attach detect configuration 8 18h r/w 46h high-speed switch configuration 8 25h r/w 14h register 10-8: general config uration register (address 15h) r/w-0 u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 alert_mask ? alert_link dschg rtn_en rtn_rst ration_beh<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 alert_mask: disables the alert# pin from asserting in the case of an error. 1 = the alert# pin will not be asserted in the event of an error condition. 0 = the alert# pin will be asserted if an error condition or indicator event is detected. bit 6 unimplemented bit 5 alert_link: links the alert# pin to be asserted when the low_cur and/or treg bits are set. 1 = the alert# pin will be asserted if the low_cur or treg indicator bit is set. 0 = the alert# pin will not be asserted if the low_cur or treg indicator bit is set. bit 4 dschg: forces the v bus to be reset and discharged when the ucs81003 is in the active state. writing this bit to a logic ? 1 ? will cause the port power switch to be opened and the discharge circuitry to activate to discharge v bus . the port power switch will remain open while this bit is ? 1 ?. this bit is not self-clearing. bit 3 rtn_en: ration enable ? enables charge rationing functionality and power monitoring. 1 = charge rationing is enabled (see section 7.4 ?battery full? ). 0 = charge rationing is disabled. the total accumulated charge registers will be cleared to 00_00h and current data will no longer be accumulated. if the total accumulated charge registers have already reached the charge rationing threshold (see section 10.6 ?charge rationing threshold registers? ), the applied response will be removed as if the charge rationing had been reset. this will also clear the ration status bit (if set).
ucs81003 ds20005334a-page 56 ? 2014 microchip technology inc. 10.4.2 emulation configuration register the contents of this register are retained in sleep. bit 2 rtn_rst: ration reset ? resets the charge rationing functionality. when this bit is set to ?1?, the total accumulated charge registers are reset to 00_00h. in addition, when this bit is set, the ration status bit will be cleared and, if there are no other errors or active indicators, the alert# pin will be released. 1 = em_en is logic 1 0 = em_en is logic 0 bit 1-0 ration_beh<1:0>: controls the behavior when the power rationing threshold is reached as shown in table 7-1 . 00 = report 01 = report and disconnect 10 = disconnect and go to sleep 11 = ignore register 10-8: general configuration register (address 15h) (continued) register 10-9: emulat ion configuration regi ster (address 16h) r/w-1 u-x u-x r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 dis_to ? ? em_to_dis em_retry em_resp em_reset_time<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 dis_to: disable timeout: disables the timeout and idle reset functionality (see section 11.2.1.6 ?smbus timeout and idle reset? ). 1 = the timeout and idle reset functionality is disabled. this is used for i 2 c compliance. 0 = the timeout and idle reset functionality is enabled. bit 6-5 unimplemented bit 4 em_to_dis: emulation timeout disable - disables the emulation circuitry timeout for all charger emu- lation profiles in the dce cycle. there is a separate bit to enable/disable the emulation timeout for the custom charger emulation profile ( register 10-35 ); however, if the em_to_dis bit is set, the emula- tion timeout will also be disabled for the custom charger emulation profile. ( note 1 ) 1 = emulation timeout is disabled during the dce cycle. the applied charger emulation profile will not exit as a result of an emulation timeout event. the i bus current will be checked continuously and if it exceeds the i bus_chg threshold for any reason, the charger emulation profile will be accepted. 0 = emulation timeout is enabled during the dce cycle. an individual charger emulation profile will be applied and maintained for the duration of the t em_timeout value. when this timer expires, the ucs81003 will determine whether the charger emulation profile was successful and take appro- priate action. bit 3 em_retry: configures whether the dce cycle will reset and restart if it reaches the final profile with- out the portable device drawing charging current and accepting one of the profiles. this bit is only used if the ucs81003 is configured to emulate a dedicated charger. 1 = once the dce cycle is completed, it will perform emulation reset and restart from the first enabled charger emulation profile in the dce cycle. 0 = once the dce cycle is completed, it will not restart. the d pout and d mout will be left as high z pins and the port power switch will be closed. the current limiting mode is determined by the custom current limiting behavior settings (see section 10.14.2 ?custom current limiting behavior configuration register? ).
? 2014 microchip technology inc. ds20005334a-page 57 ucs81003 10.4.3 switch configuration register the contents of this register are retained in sleep. bit 2 em_resp: leave emulation response - enables the dedicated charger emulation cycle mode to hold the d pout and d mout stimulus response after the ucs81003 has finished emulation using the legacy, bc1.2 dcp, or custom charger emulation profiles ( note 2 ). 1 = if a portable device begins drawing charging current while the ucs81003 is applying the bc1.2 dcp, custom or any of the legacy charger emulation profiles during the dce cycle, the last response applied will be kept in place until a removal detection event occurs, the internal tem- perature exceeds the t reg value, or emulation is restarted. in the case of the bc1.2 dcp or leg- acy 3 charger emulation profiles, this will be the short (r dcp_res ). in the case of the legacy 1, legacy 2 or legacy 4 - 7 profiles, this will be the d pout and d mout pin voltages. if a portable device does not draw charging current, the dce cycle will behave normally. 0 = the dedicated emulation circuitry will behave normally. it will remove the short condition when the t em_timeout timer has expired, regardless if the portable device has drawn charging current or not. bit 1-0 em_reset_time<1:0>: determines the length of the t em_reset time (see section 9.8.1 ?emulation reset? ) as shown below. the value selected does not include discharge time; however, this value plus discharge result in the actual reset time. 00 =50 ms 01 =75 ms 10 =125 ms 11 =175 ms note 1: if the em_to_dis bit is set and the legacy 2, legacy 4 or custom charger emulation profiles were accepted during the dce cycle, a removal is not detected. to avoid this iss ue, re-enable the emulation timeout after applying any test pro- files and charging with the 'final' profile. 2: if the hsw_dce bit is set, the high-speed switch will be cl osed regardless of the status of the em_resp bit. leaving the emulation response applied will not allow normal usb traffic. therefore, prior to setting the hsw_dce bit, this bit should be cleared. register 10-9: emulation configuration register ( address 16h) (continued) register 10-10: switch configu ration register (address 17h) r/w-0 u-x r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 pin_ign ? em_en_set m2_set m1_set s0_set pwr_ens latchs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pin_ign: ignores the m1, m2, pwr_en and em_en pin states when determining the active mode selection and power state. 1 = the active mode selection and power state will be set by the individual control bits and not by the m1, m2, pwr_en and em_en pin states. these pin states are ignored. 0 = the active mode selection and power state will be set by the or?d combination of the m1, m2, pwr_en and em_en pin states and the corresponding bit states. bit 6 unimplemented bit 5 em_en_set: in conjunction with other controls, determines the active mode that is selected (see section 9.2 ?active mode selection? ) and power state (see table 5-2 ). this bit is or?d with the em_en pin. bit 4 m2_set: in conjunction with other controls, determines the active mode that is selected (see section 9.2 ?active mode selection? ) and power state (see table 5-2 ). this bit is or?d with the m2 pin. bit 3 m1_set: in conjunction with other controls, determines the active mode that is selected (see section 9.2 ?active mode selection? ) and power state (see table 5-2 ). this bit is or?d with the m1 pin.
ucs81003 ds20005334a-page 58 ? 2014 microchip technology inc. 10.4.4 attach detection configuration resister the contents of this register are retained in sleep. bit 2 s0_set: in smbus mode, enables the attach and removal detection feature and affects the power state (see section 9.2 ?active mode selection? ). 1 = detection is enabled. also see ta bl e 5 - 2 . 0 = detection is not enabled. also see tab l e 5 - 2 . bit 1 pwr_ens: controls whether the port power switch may be turned on or not and affects the power state (see section 5.3.4 ?pwr_en input? ). this bit is or?d with the pwr_en pin and the polarity of both are controlled by sel pin decode. thus, if the polarity is set to active high, either the pwr_en pin or this bit must be ? 1 ? to enable the port power switch. bit 0 latchs: in smbus mode, controls the fault handling routine that is used in the case that an error is detected (see section 5.3.5 ?latch input? ). 1 = the ucs81003 will latch its error conditions. in order for the device to return to normal active state, the err bit must be cleared by the user. 0 = the ucs81003 will automatically retry when an error condition is detected. register 10-10: switch configuration register (address 17h) (continued) register 10-11: attach detection co nfiguration register (address 18h) r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 reserved dischg_time_sel<1:0> att_th<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 reserved: do not change. bit 3-2 dischg_time_sel<1:0>: sets the t discharge time as follows: 00 = 100 ms 01 = 200 ms 10 = 300 ms 11 = 400 ms bit 1-0 att_th<1:0>: determines the attach detection threshold (i det_qual ) and removal detection thresh- olds (i rem_qual_det and i rem_qual_act ) as shown below. ( note 1 ) 00 = 200 a attach, 100 a removal threshold 01 = 400 a attach, 300 a removal threshold 10 = 800 a attach, 700 a removal threshold 11 = 1000 a attach, 900 a removal threshold note 1: the removal threshold is different when operating in the active power state versus when operating in the detect power state.
? 2014 microchip technology inc. ds20005334a-page 59 ucs81003 10.4.5 high-speed switch configuration register the contents of this register are retained in sleep. register 10-12: high-speed switch configuration register (address 25h) u-x u-x u-x r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 ? ? ? reserved hsw_cust hsw_cdp hsw_det hsw_dce bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented bit 4 reserved: do not change. bit 3 hsw_cust: enables the usb high-speed data switch to be active during the custom handshake. this control is checked at the beginning of charger emulation. therefore, changing this control during emula- tion will have no immediate effect. upon restarting charger emulation (as a result of the em_retry bit being set, a removal detection event, or change of emulation controls), the high-speed switch will close. 1 = the usb high-speed data switch is enabled while the custom charger emulation profile is applied. also, if the custom charger emulation profile is accepted during the dedicated charger emulation cycle, the high-speed switch will stay closed. 0 = the usb high-speed data switch is disabled while the custom charger emulation profile is applied. bit 2 hsw_cdp: enables the usb high-speed data switch to be active during the cdp handshake. this con- trol is checked at the beginning of charger emulation. therefore, changing this control during emulation will have no immediate effect. upon restarting charger emulation (as a result of a removal detection event or change of emulation controls), the high-speed switch will close. 1 = the usb high-speed data switch is enabled during the cdp handshake. 0 = the usb high-speed data switch is disabled during the cdp handshake. bit 1 hsw_det: enables the usb high-speed data switch to be active during the detect power state. if the s0 control is set to ? 0 ?, this bit is ignored. 1 = the usb high-speed data switch will be closed during the detect power state. 0 = the usb high-speed data switch is open during the detect power state. bit 0 hsw_dce: enables the usb high-speed data switch after the dcp charger emulation profile or one of the legacy charger emulation profiles was accepted during the dce cycle and the portable device is charging. this bit is ignored if the ucs81003 is not in the active state. this bit will not cause the high- speed switch to be closed during emulation when the dcp and legacy profiles are applied, only after the dcp or a legacy charger emulation profile has been accepted. 1 = the usb high-speed data switch will be closed. 0 = the usb high-speed data switch will be open.
ucs81003 ds20005334a-page 60 ? 2014 microchip technology inc. 10.5 current limit register the current limit register controls the ilim used by the port power switch. the default setting is based on the resistor on the comm_sel/i lim pin and this value cannot be changed to be higher than hardware set value. the contents of this register are retained in sleep. 10.6 charge rationing threshold registers the charge rationing threshold registers set the maximum allowed charge that will be delivered to a portable device. every time the total accumulated charge registers are updated, the value is checked against this limit. if the value meets or exceeds this limit, the ration bit is set (see section 10.4.1 ?general configuration register? ) and action taken according to the ration_beh<1:0> bits (see section 10.4.1 ?general configuration register? ). the units are in mah, with a range from 0 to ~218429. the contents of this register are retained in sleep. name bits address cof default current limit 8 19h r/w 00h register 10-13: current limit register (address 19h) u-x u-x u-x u-x u-x r/w-0 r/w-0 r/w-0 ? ? ? ? ?ilim_sw<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 ilim_sw<2:0>: sets the i lim value as follows: 000 = 0.57a 001 = 1.00a 010 = 1.13a 011 = 1.35a 100 = 1.68a 101 = 2.05a 110 = 2.28a 111 = 2.85a (3.0a maximum) note 1: unless otherwise indicated, the values specified above are the typical i lim in the table 1-2 . name bits address cof default charge rationing threshold high byte 81ahr/wffh charge rationing threshold low byte 81bhr/wffh register 10-14: charge rationing threshold (address 1ah - 1bh) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chthr<15> chthr<14> chthr<13> chthr<12> chthr<11> chthr<10> chthr<9> chthr<8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chthr<7> chthr<6> chthr<5> chthr<4> chthr<3> chthr<2> chthr<1> chthr<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 chthr<15:1>: charge rationing threshold lsb = 3.333 mah
? 2014 microchip technology inc. ds20005334a-page 61 ucs81003 10.7 auto-recovery configuration register the contents of this register are retained in sleep. the auto-recovery configuration register sets the parameters used when the auto-recovery fault handling algorithm is invoked (see section 7.5.1 ?auto-recovery fault handling? ). once the auto-recovery fault handling algorithm has checked the overtemperature and back-drive condi- tions, it will set the i lim value to i test and then turn on the port power switch and start the t rst timer. if, after the timer has expired, the v bus voltage is less than v test , then it is assumed that a short-circuit condition is present and the error state is reset. name bits address cof default auto-recovery configuration 8 1ch r/w 2ah register 10-15: auto-re covery configuration re gister (address 1ch) u-x r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 ? tcycle<2:0> trst_sw<1:0> vtst_sw<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6-4 tcycle<2:0>: defines the delay (t cycle ) after the error state is entered before the auto-recovery fault handling algorithm is started as shown below. 000 = 15 ms 001 = 20 ms 010 = 25 ms 011 = 30 ms 101 = 40 ms 110 = 45 ms 111 = 50 ms bit 3-2 trst_sw<1:0>: sets the t rst time as shown as shown below. 00 = 10 ms 01 = 15 ms 10 = 20 ms 11 = 25 ms bit 1-0 vtst_sw<1:0>: sets the v test value as shown below. 00 = 250 mv 01 = 500 mv 10 =750 mv 11 = 1000 mv
ucs81003 ds20005334a-page 62 ? 2014 microchip technology inc. 10.8 ibus_chg configuration register the ibus_chg configuration register sets the i bus_chg current value. if current greater than i bus_chg is detected flowing out of v bus , emulation is successful. the bit weights are in ma, and the range is from 11.72 ma to 175.8 ma. the contents of this register are not retained in sleep. 10.9 tdet_charge configuration register the tdet_charge configuration register controls the t dc_temp and t det_charge timing. the t dc_temp timer is started whenever the temperature exceeds t reg . this timer is meant to give the system time to cool at the lower i lim setting before changing i lim again. the t det_charge timer is started whenever the v bus voltage is discharged and the bypass switch is re-activated. this timer is meant to be a delay to allow the v bus capacitor to charge before detecting an attach detection event. if t det_charge time is increased greater than 800 ms, larger bus capacitors can be accommodated; however, with a portable device present and pwr_en disabled, a removal detection event and then another attach detection event will occur. the contents of this register are retained in sleep. name bits address cof default ibus_chg configuration 81ehr/w0fh register 10-16: ibus_chg config uration register (address 1eh) u-x u-x u-x u-x r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ichg<3> ichg<2> ichg<1> ichg<0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented bit 3-0 ichg<3:0> 1 lsb = 11.72 ma name bits address cof default tdet_charge configuration 81fhr/w03h
? 2014 microchip technology inc. ds20005334a-page 63 ucs81003 10.10 preloaded emulation enable registers the preloaded emulation enable registers enable the charger emulation profiles used by the emulation circuitry. the contents of these registers are retained in sleep. register 10-17: tdet_charge config uration register (address 1fh) u-x u-x u-x r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 ? ? ? dc_temp_set<1:0> det_charge_set<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented bit 4-3 dc_temp_set<1:0>: determines the t dc_temp time as shown below. 00 = 200 ms 01 = 400 ms 10 = 800 ms 11 = 1600 ms bit 2-0 det_charge_set<2:0>: determines the t det_charge time as shown below. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1000 ms 101 = 1200 ms 110 = 1400 ms 111 = 2000 ms name bits address cof default bcs emulation enable 8 20h r/w 16h legacy emulation enable 8 21h r/w 00h register 10-18: bcs emulation enable register (address 20h) u-x u-x u-x r/w-1 u-x r/w-1 r/w-1 r/w-0 ? ? ?dcp_em_dis ? reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented bit 4 dcp_em_dis: disables the dcp charger emulation profile in the dce cycle. this bit is ignored if the m1, m2 and em_en control settings have selected dcp mode (see ta b l e 9 - 1 ). 1 = the bc1.2 dcp charger emulation profile is not enabled during the dce cycle. 0 = the bc1.2 dcp charger emulation profile is enabled during the dedicated charger emulation cycle. bit 3 unimplemented bit 2-0 reserved: do not change.
ucs81003 ds20005334a-page 64 ? 2014 microchip technology inc. 10.11 preloaded emulation timeout configuration registers the preloaded emulation timeout configuration regis- ters control the t em_timeout setting that is applied whenever the indicated preloaded charger emulation profile is applied during the dce cycle. these settings are not used if the em_to_dis bit is set. the contents of this registers are retained in sleep. register 10-19: legacy emulatio n enable register (address 21h) u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? l7em_dis l6em_dis l5em_dis l4em_dis l3em_dis l2em_dis l1em_dis bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 l7em_dis: disables the legacy 7 charger emulation profile. 1 = the legacy 7 charger emulation profile is not enabled. 0 = the legacy 7 charger emulation profile is enabled. bit 5 l6em_dis: disables the legacy 6 charger emulation profile. 1 = the legacy 6 charger emulation profile is not enabled. 0 = the legacy 6 charger emulation profile is enabled. bit 4 l5em_dis: disables the legacy 5 charger emulation profile. 1 = the legacy 5 charger emulation profile is not enabled. 0 = the legacy 5 charger emulation profile is enabled. bit 3 l4em_dis: disables the legacy 4 charger emulation profile. 1 = the legacy 4 charger emulation profile is not enabled. 0 = the legacy 4 charger emulation profile is enabled. bit 2 l3em_dis: disables the legacy 3 charger emulation profile. 1 = the legacy 3 charger emulation profile is not enabled. 0 = the legacy 3 charger emulation profile is enabled. bit 1 l2em_dis: disables the legacy 2 charger emulation profile. 1 = the legacy 2 charger emulation profile is not enabled. 0 = the legacy 2 charger emulation profile is enabled. bit 0 l1em_dis: disables the legacy 1 charger emulation profile. 1 = the legacy 1 charger emulation profile is not enabled. 0 = the legacy 1 charger emulation profile is enabled. name bits address cof default bcs emulation timeout config 8 22h r/w 10h legacy emulation timeout config 1 8 23h r/w 6ch legacy emulation timeout config 2 8 24h r/w 01h
? 2014 microchip technology inc. ds20005334a-page 65 ucs81003 register 10-20: bcs emulation timeout config register (address 22h) u-x u-x r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcp_em_to<1:0> reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 dcp_em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the bc1.2 dcp charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 00 =12.8s bit 3-0 reserved: do not change. register 10-21: legacy em ulation timeout config 1 register (address 23h) r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 l1em_to<1:0> l2em_to<1:0> l3em_to<1:0> l4em_to<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 l1em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 1 charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 =12.8s bit 5-4 l2em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 2 charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 =12.8s bit 3-2 l3em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 3 charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 =12.8s bit 1-0 l4em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 4 charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 =12.8s
ucs81003 ds20005334a-page 66 ? 2014 microchip technology inc. 10.12 preloaded emulation configuration registers the preloaded emulation configuration registers store the settings loaded from internal memory as required for the preloaded charger emulation profile that is actively being applied. these registers are read only. the legacy charger emulation profiles, the bc1.2 sdp, and the bc1.2 dcp charger emulation profile do not use the stimulus 3 configuration registers (39h - 3bh). whenever these charger emulation profiles are applied, registers 39h - 3bh will not be updated and their contents should be ignored. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and bc1.2 dcp charger emulation profiles. the contents of registers 31h, 35 and 39h are not retained in sleep. they are updated as needed. the contents of registers 32h, 33h, 34h, 36h, 37h, 38h, 3ah, 3bh, 40h are retained in sleep. 10.12.1 applied charger emulation register the contents of this register are not retained in sleep. the contents are updated as the charger emulation profile being applied changes. register 10-22: legacy em ulation timeout config 2 register (address 24h) u-x u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 ? ? l5em_to<1:0> l6em_to<1:0> l7em_to<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 l5em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 5 charger emulation profile is used dur ing the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 3-2 l6em_tov<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 6 charger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 1-0 l7em_to<1:0>: defines the t em_timeout setting, as shown below. is applied when the legacy 7 charger emulation profile is used dur ing the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s name bits address cof default applied charger emulation 8 30h r 00h preloaded emulation stimulus 1 - config 1 8 31h r 00h preloaded emulation stimulus 1 - config 2 8 32h r 26h preloaded emulation stimulus 1 - config 3 8 33h r 00h preloaded emulation stimulus 1 - config 4 8 34h r 02h preloaded emulation stimulus 2 - config 1 8 35h r 00h preloaded emulation stimulus 2 - config 2 8 36h r 09h preloaded emulation stimulus 2 - config 3 8 37h r 00h preloaded emulation stimulus 2 - config 4 8 38h r 04h preloaded emulation stimulus 3 - config 1 8 39h r 00h preloaded emulation stimulus 3 - config 2 8 3ah r 00h preloaded emulation stimulus 3 - config 3 8 3bh r 00h
? 2014 microchip technology inc. ds20005334a-page 67 ucs81003 register 10-23: applied charger em ulation register (address 30h) u-x u-x u-x u-x r-0 r-0 r-0 r-0 ? ? ? ? pre_em_sel<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented bit 3-0 pre_em_sel<3:0>: indicates which of the charger emulation profiles is being actively applied, as shown below. 0000 = data pass-through or bc1.2 sdp 0001 = bc1.2 cdp 0010 = bc1.2 dcp 0011 = legacy 1 0100 = legacy 2 0101 = legacy 3 0110 = legacy 4 0111 = legacy 5 1000 = legacy 6 1001 = legacy 7 1010 = custom profile all others = not used register 10-24: preloaded emulation stimulus 1 co nfiguration 1 register (address 31h) u-x r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? s1_td_type s1_td<2:0> stim1<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 s1_td_type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer then removed (if the stimulus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 s1_td<2:0>: determines the stimulus 1 t stim_del value as shown below. 000 =0 ms 001 =1 ms 010 =5 ms 011 =10 ms 100 =20 ms 101 =40 ms 110 =80 ms 111 =100 ms
ucs81003 ds20005334a-page 68 ? 2014 microchip technology inc. bit 2-0 stim1<2:0>: determines the stimulus 1 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting cannot be used for the d mout port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is higher than the threshold (s1_th). 010 = window comparator. d pout voltage is lower than the threshold (s1_th) and d pout voltage higher than the fixed threshold. 011 =d mout voltage is higher than the threshold (s1_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is higher than the threshold (s1_th). 111 =v bus voltage is present after port power switch is closed. next stimulus will not wait for this to be removed. register 10-25: preloaded emulation stimulus 1 co nfiguration 2 register (address 32h) r-0 r-0 r-1 r-0 r-0 r-1 r-1 r-0 s1_r1mag<3:0> s1_r1<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 s1_r1mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any fiel d that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for s1_r1 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the s1_r1mag bits specify the voltage relative to ground: ? for s1_r1 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the s1_r1mag bits specify the resistor value: ? for s1_r1 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the s1_r1mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): register 10-24: preloaded emulation stimulus 1 co nfiguration 1 register (address 31h) (continued) 0000 = pull down 0110 = 600 mv 1100 = 1800 mv 0001 =400mv 0111 = 700 mv 1101 = 2000 mv 0010 =400mv 1000 = 800 mv 1110 = 2200 mv 0011 =400mv 1001 = 900 mv 1111 = do not use 0100 =400mv 1010 = 1400 mv 0101 =500mv 1011 = 1600 mv 0000 =1.8k ? 0110 =40k ? 1100 =100k ? 0001 =10k ? 0111 =43k ? 1101 =120k ? 0010 =15k ? 1000 =50k ? 1110 =150k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 = 200 k ? 1100 =200k ? 0001 =100k ? 0111 = 200 k ? 1101 =200k ? 0010 =125k ? 1000 =93k ? 1110 =200k ? 0011 =150k ? 1001 = 100 k ? 1111 = do not use 0100 =200k ? 1010 = 125 k ? 0101 =200k ? 1011 = 150 k ?
? 2014 microchip technology inc. ds20005334a-page 69 ucs81003 bit 3-0 s1_r1<3:0>: defines the stimulus response as shown below:. 0000 = remove previous response on d pout and d mout 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if stim1 = 000, the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are not removed. if stim1 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emula- tion reset are removed. for all other stim1 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if stim1<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. ot herwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if stim1<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. ot herwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-26: preloaded emulation stimulus 1 co nfiguration 3 register (address 33h)( note 1 ) u-x u-x r-0 r-0 r-0 r-0 r-0 r-0 ? ? s1_pupd<1:0> s1_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 s1_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down ( 0000b ). the bit decode is given below. 00 = 10 a 01 = 50 a 10 = 100 a 11 = 150 a register 10-25: preloaded emulation stimulus 1 co nfiguration 2 register (address 32h) (continued)
ucs81003 ds20005334a-page 70 ? 2014 microchip technology inc. bit 3-0 s1_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus is v bus voltage is ready to be applied or applied (i.e., stim1<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. register 10-27: preloaded emulation stimulus 1 co nfiguration 4 register (address 34h)( note 1 ) u-x u-x u-x u-x u-x r-0 r-1 r-0 ? ? ? ? ? s1_ratio<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 s1_ratio<2:0>: determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., s1_r1<3:0> = 0110b , 1001b , or 1100b ). 000 =0.25 001 =0.33 010 =0.4 011 =0.5 100 =0.54 101 =0.6 110 =0.66 111 = do not use. note 1: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are only used by the legacy charger emulation profiles. register 10-26: preloaded emulation stimulus 1 co nfiguration 3 register (address 33h)( note 1 ) (continued)
? 2014 microchip technology inc. ds20005334a-page 71 ucs81003 register 10-28: preloaded emulation stimulus 2 co nfiguration 1 register (address 35h) u-x r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? s2_td_type s2_td<2:0> stim2<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 s2_td_type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer, then removed (if the stimu- lus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 s2_td<2:0>: determines the stimulus 2 t stim_del value as shown below: 000 =0 ms 001 =1 ms 010 =5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 stim2<2:0>: determines the stimulus 2 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting cannot be used for the dm out port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is greater than the threshold (s2_th). 010 = window comparator. d pout voltage is lower than the threshold (s2_th) and d pout voltage greater than the fixed threshold. 011 =d mout voltage is greater than the threshold (s2_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is greater than the threshold (s2_th). 111 = voltage is present after the port power switch is closed. next stimulus will not wait for this to be removed.
ucs81003 ds20005334a-page 72 ? 2014 microchip technology inc. register 10-29: preloaded emulation stimulus 2 co nfiguration 2 register (address 36h) r-0 r-0 r-0 r-0 r-1 r-0 r-0 r-1 s2_r2mag<3:0> s2_r2<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 s2_r2mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for s2_r2 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the s2_r2mag bits specify the voltage relative to ground: ? for s2_r2 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the s2_r2mag bits specify the resistor value: ? for s2_r2 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the s2_r2mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): 0000 = pull down 0110 = 600 mv 1100 = 1800 mv 0001 =400mv 0111 = 700 mv 1101 = 2000 mv 0010 =400mv 1000 = 800 mv 1110 = 2200 mv 0011 =400mv 1001 = 900 mv 1111 = do not use 0100 =400mv 1010 = 1400 mv 0101 =500mv 1011 = 1600 mv 0000 =1.8k ? 0110 =40k ? 1100 =100k ? 0001 =10k ? 0111 =43k ? 1101 =120k ? 0010 =15k ? 1000 =50k ? 1110 =150k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 = 200 k ? 1100 =200k ? 0001 =100k ? 0111 = 200 k ? 1101 =200k ? 0010 =125k ? 1000 =93k ? 1110 =200k ? 0011 =150k ? 1001 = 100 k ? 1111 = do not use 0100 =200k ? 1010 = 125 k ? 0101 =200k ? 1011 = 150 k ?
? 2014 microchip technology inc. ds20005334a-page 73 ucs81003 bit 3-0 s2_r2<3:0>: defines the stimulus response as shown below: 0000 = remove previous response on d pout and d mout 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if stim2 = 000 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are not removed. if stim2 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are removed. for all other stim2 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if stim2<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. otherwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if stim2<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. otherwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-30: preloaded emulation stimulus 2 co nfiguration 3 register (address 37h)( note 1 ) u-x u-x r-0 r-0 r-0 r-0 r-0 r-0 ? ? s2_pupd<1:0> s2_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 s2_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down ( 0000b ). the bit decode is as follows: 00 =10 a 01 =50 a 10 =100 a 11 =150 a register 10-29: preloaded emulation stimulus 2 co nfiguration 2 register (address 36h) (continued)
ucs81003 ds20005334a-page 74 ? 2014 microchip technology inc. bit 3-0 s2_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus v bus voltage is ready to be applied or applied (i.e., stim2<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. register 10-31: preloaded emulation stimulus 2 co nfiguration 4 register (address 38h)( note 1 ) u-x u-x u-x u-x u-x r-1 r-0 r-0 ? ? ? ? ? s2_ratio<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 s2_ratio<2:0>: determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., s2_r2<3:0> = 0110b , 1001b , or 1100b ). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = do not use. note 1: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are only used by the legacy charger emulation profiles. register 10-30: preloaded emulation stimulus 2 co nfiguration 3 register (address 37h)( note 1 ) (continued)
? 2014 microchip technology inc. ds20005334a-page 75 ucs81003 register 10-32: preloaded emulation stimulus 3 co nfiguration 1 register (address 39h) u-x r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? s3_td_type s3_td<2:0> stim3<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 s3_td_type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 s3_td<2:0>: determines the stimulus 3 t stim_del value as shown below: 000 =0 ms 001 =1 ms 010 =5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 stim3<2:0>: determines the stimulus 3 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting cannot be used for the dm out port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is greater than the threshold (s3_th). 010 = window comparator. d pout voltage is less than the threshold (s3_th) and d pout voltage greater than the fixed threshold. 011 =d mout voltage is greater than the threshold (s3_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is greater than the threshold (s3_th). 111 = voltage is present after the port power switch is closed. next stimulus will not wait for this to be removed.
ucs81003 ds20005334a-page 76 ? 2014 microchip technology inc. register 10-33: preloaded emulation stimulus 3 co nfiguration 2 register (address 3ah) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 s3_r3mag<3:0> s3_r3<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 s3_r3mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for s3_r3 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the s3_r3mag bits specify the voltage relative to ground: ? for s3_r3 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the s3_r3mag bits specify the resistor value: ? for s3_r3 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the s3_r3mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): 0000 = pull down 0110 =600mv 1100 = 1800 mv 0001 = 400 mv 0111 =700mv 1101 = 2000 mv 0010 = 400 mv 1000 =800mv 1110 = 2200 mv 0011 = 400 mv 1001 =900mv 1111 = do not use 0100 = 400 mv 1010 =1400mv 0101 = 500 mv 1011 =1600mv 0000 =1.8k ? 0110 =40k ? 1100 = 100 k ? 0001 =10k ? 0111 =43k ? 1101 = 120 k ? 0010 =15k ? 1000 =50k ? 1110 = 150 k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 =200k ? 1100 = 200 k ? 0001 = 100 k ? 0111 =200k ? 1101 = 200 k ? 0010 = 125 k ? 1000 =93k ? 1110 = 200 k ? 0011 = 150 k ? 1001 =100k ? 1111 = do not use 0100 = 200 k ? 1010 =125k ? 0101 = 200 k ? 1011 =150k ?
? 2014 microchip technology inc. ds20005334a-page 77 ucs81003 bit 3-0 s3_r3<3:0>: defines the stimulus response as shown below: 0000 = remove previous response on d pout and d mout 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if stim3 = 000 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are not removed. if stim3 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are removed. for all other stim3 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if stim3<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. otherwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if stim3<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. otherwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-34: preloaded emulation stimulus 3 co nfiguration 3 register (address 3bh)( note 1 ) u-x u-x r-0 r-0 r-0 r-0 r-0 r-0 ? ? s3_pupd<1:0> s3_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 s3_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down ( 0000b ). the bit decode is as follows: 00 =10 a 01 =50 a 10 =100 a 11 =150 a register 10-33: preloaded emulation stimulus 3 co nfiguration 2 register (address 3ah) (continued)
ucs81003 ds20005334a-page 78 ? 2014 microchip technology inc. 10.13 custom emulation configuration registers the custom emulation configuration registers store the values used by the custom charger emulation cir- cuitry. the custom charger emulation profile is set up as three stimuli and the respective responses. the contents of registers 40h to 4ch are retained in sleep. bit 3-0 s3_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus is v bus voltage is ready to be applied or applied (i.e., stim3<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. name bits address cof default custom emulation config 8 40h r/w 01h custom emulation stimulus 1 - config 1 8 41h r/w 00h custom emulation stimulus 1 - config 2 8 42h r/w 00h custom emulation stimulus 1 - config 3 8 43h r/w 00h custom emulation stimulus 1 - config 4 8 44h r/w 00h custom emulation stimulus 2 - config 1 8 45h r/w 00h custom emulation stimulus 2 - config 2 8 46h r/w 00h custom emulation stimulus 2 - config 3 8 47h r/w 00h custom emulation stimulus 2 - config 4 8 48h r/w 00h custom emulation stimulus 3 - config 1 8 49h r/w 00h custom emulation stimulus 3 - config 2 8 4ah r/w 00h custom emulation stimulus 3 - config 3 8 4bh r/w 00h custom emulation stimulus 3 - config 3 8 4ch r/w 00h register 10-34: preloaded emulation stimulus 3 co nfiguration 3 register (address 3bh)( note 1 ) (continued)
? 2014 microchip technology inc. ds20005334a-page 79 ucs81003 register 10-35: custom emulation co nfiguration register (address 40h) u-x u-x r/w-0 r/w-0 r/w-0 r/w-0 r-0 r/w-1 ? ? cs_to_dis cs_em_to<1:0> cs_frst reserved csem_dis bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5 cs_to_dis: disables the emulation timeout timer when the custom charger emulation profile is applied during the dce cycle. if the em_to_dis is set, this bit will have no effect ( note 1 ). 1 = the emulation timeout timer is disabled when the custom charger emulation profile is applied during the dce cycle. when the custom charger emulation profile is being applied, the ucs81003 will be constantly monitoring the i bus current. when the i bus current is greater than i bus_chg , regardless of the reason, then the custom charger emulation profile will accepted. if the portable device does not draw more than i bus_chg current, then the ucs81003 will continue waiting until this bit is cleared. 0 = the emulation timeout timer is enabled when the custom charger emulation profile is applied during the dce cycle and the em_to_dis bit is not set bit 4-3 cs_em_to<1:0>: determines the t em_timeout value, as shown below. is used when the custom char- ger emulation profile is used during the dce cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 2 cs_frst: disables the custom charger emulation profile. 1 = the custom charger emulation profile is the first of the profiles applied during the dce cycle. 0 = the custom charger emulation profile is the last of the profiles applied during the dce cycle. bit 1 reserved: do not change. this bit will read ? 0 ? and should not be written to a logic ? 1 ?. bit 0 csem_dis: determines whether the custom charger emulation profile is placed first or last in the dce cycle. 1 = the custom charger emulation profile is not enabled. 0 = the custom charger emulation profile is enabled. note 1: if the cs_to_dis bit is set and the custom charger emulation profile was accepted during the dce cycle, a removal is not detected. to avoid this issue, re-enable the emulation timeout after applying any test pro- files and charging with the 'final' profile.
ucs81003 ds20005334a-page 80 ? 2014 microchip technology inc. register 10-36: custom emulation st imulus 1 configurat ion 1 register (address 41h) u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w--0 r/w--0 r/w--0 ? cs_s1type cs_s1_td<2:0> cs_stim1<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 cs_s1type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer then removed (if the stimulus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 cs_s1_td<2:0>: determines the stimulus 1 t stim_del value as shown below. 000 =0 ms 001 =1 ms 010 =5 ms 011 =10 ms 100 =20 ms 101 =40 ms 110 =80 ms 111 =100 ms bit 2-0 cs_stim1<2:0>: determines the stimulus 1 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting can- not be used for the d mout port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is greater than the threshold (cs_s1_th). 010 = window comparator. d pout voltage is lower than the threshold (cs_s1_th) and d pout voltage greater than the fixed threshold. 011 =d mout voltage is greater than the threshold (cs_s1_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is greater than the threshold (cs_s1_th). 111 =v bus voltage is present after port power switch is closed. next stimulus will not wait for this to be removed.
? 2014 microchip technology inc. ds20005334a-page 81 ucs81003 register 10-37: custom emulation st imulus 1 configurat ion 2 register (address 42h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs_s1_r1mag<3:0> cs_s1_r1<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 cs_s1_r1mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for cs_s1_r1 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the cs_s1_r1mag bits specify the voltage relative to ground: ? for cs_s1_r1 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the cs_s1_r1mag bits specify the resistor value: ? for cs_s1_r1 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the cs_s1_r1mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): 0000 = pull down 0110 =600mv 1100 = 1800 mv 0001 = 400 mv 0111 =700mv 1101 = 2000 mv 0010 = 400 mv 1000 =800mv 1110 = 2200 mv 0011 = 400 mv 1001 =900mv 1111 = do not use 0100 = 400 mv 1010 =1400mv 0101 = 500 mv 1011 =1600mv 0000 =1.8k ? 0110 =40k ? 1100 = 100 k ? 0001 =10k ? 0111 =43k ? 1101 = 120 k ? 0010 =15k ? 1000 =50k ? 1110 = 150 k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 =200k ? 1100 = 200 k ? 0001 = 100 k ? 0111 =200k ? 1101 = 200 k ? 0010 = 125 k ? 1000 =93k ? 1110 = 200 k ? 0011 = 150 k ? 1001 =100k ? 1111 = do not use 0100 = 200 k ? 1010 =125k ? 0101 = 200 k ? 1011 =150k ?
ucs81003 ds20005334a-page 82 ? 2014 microchip technology inc. bit 3-0 cs_s1_r1<3:0>: defines the stimulus response as shown below: 0000 = remove previous response on d pout and d mout . 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if cs_stim1 = 000 , the 15 k ?? pull down resistors applied to d pout and d mout during emu- lation reset are not removed. if cs_stim1 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are removed. for all other cs_stim1 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if cs_stim1<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. otherwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if cs_stim1<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. otherwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-38: custom emulation stim ulus 1 configuration 3 register (address 43h)( note 1 ) u-x u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cs_s1_pupd<1:0> cs_s1_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 cs_s1_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull- down ( 0000b ). the bit decode is given below. 00 = 10 a 01 = 50 a 10 = 100 a 11 = 150 a register 10-37: custom emulation st imulus 1 configurat ion 2 register (address 42h) (continued)
? 2014 microchip technology inc. ds20005334a-page 83 ucs81003 bit 3-0 cs_s1_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus is v bus voltage is ready to be applied or applied (i.e., cs_stim1<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. register 10-39: custom emulation st imulus 1 configurat ion 4 register (address 44h)( note 1 ) u-x u-x u-x u-x u-x r/w-0 r/w-0 r/w-0 ? ? ? ? ? cs_s1_ratio<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 cs_s1_ratio<2:0>: determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., cs_s1_r1<3:0> = 0110b , 1001b , or 1100b ). 000 =0.25 001 =0.33 010 =0.4 011 =0.5 100 =0.54 101 =0.6 110 =0.66 111 = do not use. note 1: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are only used by the legacy charger emulation profiles. register 10-38: custom emulation stim ulus 1 configuration 3 register (address 43h)( note 1 ) (continued)
ucs81003 ds20005334a-page 84 ? 2014 microchip technology inc. register 10-40: custom emulation st imulus 2 configurat ion 1 register (address 45h) u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cs_s2type cs_s2_td<2:0> cs_stim2<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 cs_s2type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 cs_s2_td<2:0>: determines the stimulus 2 t stim_del value as shown below: 000 =0 ms 001 =1 ms 010 =5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 cs_stim2<2:0>: determines the stimulus 2 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting cannot be used for the dm out port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is greater than the threshold (cs_s2_th). 010 = window comparator. d pout voltage is less than the threshold (s1_th) and d pout voltage greater than the fixed threshold. 011 =d mout voltage is greater than the threshold (cs_s2_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is greater than the threshold (cs_s2_th). 111 = voltage is present after the port power switch is closed. next stimulus will not wait for this to be removed.
? 2014 microchip technology inc. ds20005334a-page 85 ucs81003 register 10-41: custom emulation st imulus 2 configurat ion 2 register (address 46h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs_s2_r2mag<3:0> cs_s2_r2<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 cs_s2_r2mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for cs_s2_r2 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the cs_s2_r2mag bits specify the voltage relative to ground: ? for cs_s2_r2 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the cs_s2_r2mag bits specify the resistor value: ? for cs_s2_r2 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the cs_s2_r2mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): 0000 = pull down 0110 =600mv 1100 = 1800 mv 0001 = 400 mv 0111 =700mv 1101 = 2000 mv 0010 = 400 mv 1000 =800mv 1110 = 2200 mv 0011 = 400 mv 1001 =900mv 1111 = do not use 0100 = 400 mv 1010 =1400mv 0101 = 500 mv 1011 =1600mv 0000 =1.8k ? 0110 =40k ? 1100 = 100 k ? 0001 =10k ? 0111 =43k ? 1101 = 120 k ? 0010 =15k ? 1000 =50k ? 1110 = 150 k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 =200k ? 1100 = 200 k ? 0001 = 100 k ? 0111 =200k ? 1101 = 200 k ? 0010 = 125 k ? 1000 =93k ? 1110 = 200 k ? 0011 = 150 k ? 1001 =100k ? 1111 = do not use 0100 = 200 k ? 1010 =125k ? 0101 = 200 k ? 1011 =150k ?
ucs81003 ds20005334a-page 86 ? 2014 microchip technology inc. bit 3-0 cs_s2_r2<3:0>: defines the stimulus response as shown below: 0000 = remove previous response on d pout and d mout 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if cs_stim2 = 000 , the 15 k ?? pull down resistors applied to d pout and d mout during emu- lation reset are not removed. if cs_stim2 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are removed. for all other cs_stim2 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if cs_stim2<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. otherwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if cs_stim2<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. otherwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-42: custom emulation stim ulus 2 configuration 3 register (address 47h)( note 1 ) u-x u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cs_s2_pupd<1:0> cs_s2_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 cs_s2_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull- down ( 0000b ). the bit decode is as follows: 00 =10 a 01 =50 a 10 =100 a 11 =150 a register 10-41: custom emulation st imulus 2 configurat ion 2 register (address 46h) (continued)
? 2014 microchip technology inc. ds20005334a-page 87 ucs81003 bit 3-0 cs_s2_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus is v bus voltage is ready to be applied or applied (i.e., cs_stim2<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. register 10-43: custom emulation st imulus 2 configurat ion 4 register (address 48h)( note 1 ) u-x u-x u-x u-x u-x r/w-0 r/w-0 r/w-0 ? ? ? ? ? cs_s2_ratio<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 cs_s2_ratio<2:0>: determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., cs_s2_r2<3:0> = 0110b , 1001b , or 1100b ). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = do not use. note 1: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are only used by the legacy charger emulation profiles. register 10-42: custom emulation stim ulus 2 configuration 3 register (address 47h)( note 1 ) (continued)
ucs81003 ds20005334a-page 88 ? 2014 microchip technology inc. register 10-44: custom emulation st imulus 3 configurat ion 1 register (address 49h) u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cs_s3type cs_s3_td<2:0> cs_stim3<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented bit 6 cs_s3type: determines the behavior of the stimulus timer. 1 = the stimulus timer controls how long the response is applied after the stimulus is detected. the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed). 0 = the stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 cs_s3_td<2:0>: determines the stimulus 3 t stim_del value as shown below: 000 =0 ms 001 =1 ms 010 =5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 cs_stim3<2:0>: determines the stimulus 3 that is used as shown below. note that the lower threshold for the window comparator option is fixed at 400 mv and only applies to the d pout pin. this setting can- not be used for the dm out port. 000 =v bus voltage ready to be applied before port power switch is closed. next stimulus will not wait for this to be removed. 001 = d pout voltage is greater than the threshold (cs_s3_th). 010 = window comparator. d pout voltage is lower than the threshold (cs_s3_th) and d pout voltage greater than the fixed threshold. 011 =d mout voltage is greater than the threshold (cs_s3_th). 100 = do not use. 101 = do not use. 110 =d pout voltage is greater than the threshold (cs_s3_th). 111 = voltage is present after the port power switch is closed. next stimulus will not wait for this to be removed.
? 2014 microchip technology inc. ds20005334a-page 89 ucs81003 register 10-45: custom emulation st imulus 3 configurat ion 2 register (address 4ah) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs_s3_r3mag<3:0> cs_s3_r3<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 cs_s3_r3mag<3:0>: determines the magnitude of the response to the stimulus. the bit decode changes meaning based on which response was selected. data written to any field that is identified as ?do not use? will not be accepted. the data will not be updated and the settings will remain set at the previous value. ? for cs_s3_r3 settings 0000 - 0011 , the response is a voltage applied on d pout /d mout pins. the cs_s3_r3mag bits specify the voltage relative to ground: ? for cs_s3_r3 settings 0100 , 0111 , 1101 - 1111 , the response is a resistor connected on d pout /d mout to gnd or v bus . the cs_s3_r3mag bits specify the resistor value: ? for cs_s3_r3 settings 0110 , 1001 , 1100 , the response is a voltage divider applied from v bus to gnd with ?center? at d pout /d mout . the cs_s3_r3mag bits specify the minimum resistance of the voltage divider (sum of r1 + r2): 0000 = pull down 0110 =600mv 1100 = 1800 mv 0001 = 400 mv 0111 =700mv 1101 = 2000 mv 0010 = 400 mv 1000 =800mv 1110 = 2200 mv 0011 = 400 mv 1001 =900mv 1111 = do not use 0100 = 400 mv 1010 =1400mv 0101 = 500 mv 1011 =1600mv 0000 =1.8k ? 0110 =40k ? 1100 = 100 k ? 0001 =10k ? 0111 =43k ? 1101 = 120 k ? 0010 =15k ? 1000 =50k ? 1110 = 150 k ? 0011 =20k ? 1001 =60k ? 1111 = do not use 0100 =25k ? 1010 =75k ? 0101 =30k ? 1011 =80k ? 0000 =93k ? 0110 =200k ? 1100 = 200 k ? 0001 = 100 k ? 0111 =200k ? 1101 = 200 k ? 0010 = 125 k ? 1000 =93k ? 1110 = 200 k ? 0011 = 150 k ? 1001 =100k ? 1111 = do not use 0100 = 200 k ? 1010 =125k ? 0101 = 200 k ? 1011 =150k ?
ucs81003 ds20005334a-page 90 ? 2014 microchip technology inc. bit 3-0 cs_s3_r3<3:0>: defines the stimulus response as shown below: 0000 = remove previous response on d pout and d mout 0001 = apply voltage on d pout ( note 1 ). 0010 = apply voltage on d mout ( note 2 ). 0011 = apply voltage on d pout and d mout . 0100 = connect resistor from d pout to gnd ( note 1 ). 0101 = do not use. 0110 = connect voltage divider from v bus to gnd with ?center? at d pout ( note 1 ). 0111 = connect resistor form d mout to gnd ( note 2 ). 1000 = do not use. 1001 = connect voltage divider from v bus to gnd with ?center? at d mout ( note 2 ). 1010 = connect ? 200 ?? resistor from d pout to d mout . 1011 = do not use. 1100 = connect voltage divider from v bus to gnd with ?center? at d pout and d mout . 1101 = connect resistor from d pout to gnd and d mout to gnd. 1110 = if cs_stim3 = 000 , the 15 k ?? pull down resistors applied to d pout and d mout during emu- lation reset are not removed. if cs_stim3 = 111 , the 15 k ?? pull down resistors applied to d pout and d mout during emulation reset are removed. for all other cs_stim3 settings, whatever was applied is not changed. 1111 = same as 1110 case above. note 1: if cs_stim3<2:0> = 000b and no other response was applied to the d pout pin, the 15 k ? pull-down resistor applied to the d pout pin during emulation reset is not removed. otherwise, the previous response is left on the d pout pin (if applicable) or the 15 k ? pull-down resistor is removed. 2: if cs_stim3<2:0> = 000b and no other response was applied to the d mout pin, the 15 k ? pull-down resistor applied to the d mout pin during emulation reset is not removed. otherwise, the previous response is left on the d mout pin (if applicable) or the 15 k ? pull-down resistor is removed. register 10-46: custom emulation stim ulus 3 configuration 3 register (address 4bh)( note 1 ) u-x u-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cs_s3_pupd<1:0> cs_s3_th<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented bit 5-4 cs_s3_pupd<1:0>: determines the magnitude of the pull-down current applied on the d pout and d mout pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull- down ( 0000b ). the bit decode is as follows: 00 =10 a 01 =50 a 10 =100 a 11 =150 a register 10-45: custom emulation st imulus 3 configurat ion 2 register (address 4ah) (continued)
? 2014 microchip technology inc. ds20005334a-page 91 ucs81003 bit 3-0 cs_s3_th<3:0>: defines the threshold value, as shown below for the specified stimulus. if the stimulus is v bus voltage is ready to be applied or applied (i.e., cs_stim3<2:0> = 000b or 111b ), the threshold value is ignored. 0000 = 400 mv 0001 = 400 mv 0010 = 400 mv 0011 = 300 mv 0100 = 400 mv 0101 = 500 mv 0110 = 600 mv 0111 = 700 mv 1000 = 800 mv 1001 = 900 mv 1010 = 1400 mv 1011 = 1600 mv 1100 = 1800 mv 1101 = 2000 mv 1110 = 2200 mv 1111 = do not use. note 1: the legacy charger emulation profiles do not use these settings. whenever a legacy charger emulation profile is applied within the dce cycle, these controls will not be updated and should be ignored. these settings are only used by the bc1.2 cdp and dcp charger emulation profiles. register 10-47: custom emulation stim ulus 3 configuration 4 register (address 4ch)( note 1 ) u-x u-x u-x u-x u-x r/w-0 r/w-0 r/w-0 ? ? ? ? ? cs_s3_ratio<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented bit 2-0 cs_s3_ratio<2:0>: determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., cs_s3_r3<2:0> = 0110b , 1001b , or 1100b ). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = do not use note 1: the bc1.2 dcp and cdp charger emulation profiles do not use this control. whenever the bc1.2 cdp or dcp charger emulation profile is applied, these controls will not be updated and should be ignored. these settings are only used by the legacy charger emulation profiles. register 10-46: custom emulation stim ulus 3 configuration 3 register (address 4bh)( note 1 ) (continued)
ucs81003 ds20005334a-page 92 ? 2014 microchip technology inc. 10.14 current limiting behavior configuration registers 10.14.1 applied current limiting behavior register the applied current limiting behavior register stores the values used by the applied current limiting mode (trip or cc) when the custom settings are not used. the contents of this register are updated automatically when charger emulation is completed. name bits address cof default applied current limiting behavior 850hr82h custom current limiting behavior config 851hr/w82h register 10-48: applied current limiting behavior register (address 50h) r-1 r-0 u-x r-0 r-0 r-0 r-1 r-0 sel_vbus_min<1:0> ? sel_r2_imin<2:0> reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 sel_vbus_min<1:0>: define the v bus_min voltage as follows: 00 = 1.5v 01 = 1.75v 10 = 2.0v 11 = 2.25v bit 5 unimplemented bit 4-2 sel_r2_imin<2:0>: define the i bus_r2min current as follows: 000 = 120 ma 001 = 570 ma 010 = 1000 ma 011 = 1350 ma 100 = 1680 ma 101 = 2050 ma bit 1-0 reserved: do not change. note 1: the values specified above are the typical ones..
? 2014 microchip technology inc. ds20005334a-page 93 ucs81003 10.14.2 custom current limiting behavior configuration register the custom current limiting behavior configuration register allows programming of current limit parameters. these controls are used when a portable device handshakes using the legacy charger emulation profiles (except legacy 3), the custom charger emulation profile, or does not handshake as a dedicated charger (i.e., a power thief). the contents of this register are retained in sleep. register 10-49: custom current limiting behavior config register (address 51h) r/w-1 r/w-0 u-x r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 cs_vbus_min<1:0> ? cs_r2_imin<2:0> reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 cs_vbus_min<1:0>: defines the custom v bus_min voltage as shown below. note that v bus_min is checked even when operating with trip current limiting. 00 = 1.5v 01 = 1.75v 10 = 2.0v 11 = 2.25v bit 5 unimplemented bit 4-2 cs_r2_imin<2:0>: define the custom i bus_r2min threshold as shown below. the default is 120 ma. this value is used under the following conditions: when a portable device handshakes using the legacy charger emulation profiles (except legacy 3) the custom charger emulation profile or when it does not handshake in dce cycle (i.e., a power thief). under these conditions, the current limiting mode is deter- mined by the relative value of i bus_r2min and ilim. when i bus_r2min 1.68 a, trip current limiting used; otherwise, cc mode is used. define the i bus_r2min current as follows: 000 = 120 ma 001 = 570 ma 010 = 1000 ma 011 = 1350 ma 100 = 1680 ma 101 = 2050 ma bit 1-0 reserved: do not change. note 1: the values specified above are the typical ones..
ucs81003 ds20005334a-page 94 ? 2014 microchip technology inc. 10.15 product id register the product id register stores a unique 8-bit value that identifies the ucs device family. 10.16 manufacturer id register the manufacturer id register stores a unique 8-bit value that identifies microchip technology inc. 10.17 revision register the revision register stores an 8-bit value that represents the part revision. name bits address cof default product id 8 fdh r 4eh name bits address cof default manufacturer id 8 feh r 5dh name bits address cof default revision 8 ffh r 82h
? 2014 microchip technology inc. ds20005334a-page 95 ucs81003 11.0 communications 11.1 operating mode the ucs81003 can operate in smbus mode (see section 11.2 ?smbus operating mode? ) or stand- alone mode (see section 11.3 ?stand-alone operating mode? ). the resistor on the comm_sel/i lim pin determines the operating mode and the hardware-set i lim setting, as shown in table 11-1 . unless connected to gnd or v dd , the resistors in table 11-1 are pull-down resistors. 11.2 smbus operating mode when the comm_sel/i lim pin is connected directly to ground or though a pull-down resistor with a value of 33 k ? or below as listed in table 11-1 , the ucs81003 communicates via the smbus or i 2 c communications protocols. note: if it is necessary to connect the comm_sel/i lim pin to v dd via a pull-up resistor, it is recommended that this resistor value not exceed 100 k ? . table 11-1: ucs81003 communication mode and i lim selection ( note 1 ) selection resistor 5% i lim setting communications mode gnd 570 ma smbus - see section 11.2.1.2 10 k ? pull-down 1000 ma smbus - see section 11.2.1.2 12 k ? pull-down 1130 ma smbus - see section 11.2.1.2 15 k ? pull-down 1350 ma smbus - see section 11.2.1.2 18 k ? pull-down 1680 ma smbus - see section 11.2.1.2 22 k ? pull-down 2050 ma smbus - see section 11.2.1.2 27 k ?? pull-down 2280 ma smbus - see section 11.2.1.2 33 k ? pull-down 2850 ma (3000 ma maximum) smbus - see section 11.2.1.2 47 k ? pull-down 570 ma stand-alone mode 56 k ? pull-down 1000 ma stand-alone mode 68 k ? pull-down 1130 ma stand-alone mode 82 k ? pull-down 1350 ma stand-alone mode 100 k ? pull-down 1680 ma stand-alone mode 120 k ? pull-down 2050 ma stand-alone mode 150 k ? pull-down 2280 ma stand-alone mode v dd (if a pull-up resistor is used, its value must not exceed 100 k ? .) 2850 ma (3000 ma maximum) stand-alone mode note 1: unless otherwise indicated, the values specified in this table are the typical i lim in table 1-2 . note 1: upon power-up, the ucs81003 will not respond to any smbus communications for 5.5 ms. after this time, full functionality is available. 2: when in the sleep state, the first smbus read command sent to the ucs81003 device address will wake it. any data sent to the ucs81003 will be ignored and any data read from the ucs81003 should be considered invalid. the ucs81003 will be fully functional 3 ms after this first read command is sent. see section 5.1.2 ?sleep state operation? .
ucs81003 ds20005334a-page 96 ? 2014 microchip technology inc. 11.2.1 system management bus in smbus mode, the ucs81003 communicates with a host controller. the smbus is a two-wire serial communication protocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 11-1 . stretching of the smclk signal is supported; however, the ucs81003 will not stretch the clock signal. figure 11-1: smbus timing diagram. 11.2.1.1 smbus start bit the smbus start bit is defined as a transition of the smbus data line from a logic ? 1 ? state to a logic ? 0 ? state while the smbus clock line is in a logic ? 1 ? state. 11.2.1.2 smbus address and rd/wr bit the smbus address byte consists of the 7-bit client address followed by the rd/wr indicator bit. if this rd/wr bit is a logic ? 0 ?, the smbus host is writing data to the client device. if this rd/wr bit is a logic ? 1 ?, the smbus host is reading data from the client device. the smbus address is determined based on the resistor connected on the sel pin as shown in ta bl e 11 - 2 . smdata smclk t buf p s s - start condition p - stop condition p s t high t low t hd:sta t su:sto t hd:sta t hd:dat t su:dat t su:sta t fall t rise note: if it is necessary to connect the sel pin to v dd via a resistor, the pull-up resistor may be any value up to 100 k ? . table 11-2: sel pin decode resistor (5%) pwr_en polarity smbus address gnd active low 1010_111(r/w ) 10 k ? pull-down active low 1010_110(r/w ) 12 k ? pull-down active low 1010_101(r/w ) 15 k ? pull-down active low 1010_100(r/w ) 18 k ? pull-down active low 0110_000(r/w ) 22 k ? pull-down active low 0110_001(r/w ) 27 k ? pull-down active low 0110_010(r/w ) 33 k ? pull-down active low 0110_011(r/w ) 47 k ? pull-down active high 0110_011(r/w ) 56 k ? pull-down active high 0110_010(r/w ) 68 k ? pull-down active high 0110_001(r/w ) 82 k ? pull-down active high 0110_000(r/w ) 100 k ? pull-down active high 1010_100(r/w ) 120 k ? pull-down active high 1010_101(r/w ) 150 k ? pull-down active high 1010_110(r/w ) v dd (if a pull-up resistor is used, its value must not exceed 100 k ? ) active high 1010_111(r/w )
? 2014 microchip technology inc. ds20005334a-page 97 ucs81003 11.2.1.3 smbus data bytes all smbus data bytes are sent most significant bit first and composed of eight bits of information. 11.2.1.4 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives. this is done by the client device pulling the smbus data line low after the 8 th bit of each byte that is transmitted. this applies to both the write byte and block write protocols. by holding the smbus data line high after the 8 th data bit has been sent, the host will nack (not acknowledge) the last data byte to be received from the client. for the block read protocol, the host will ack each data byte that it receives except the last data byte. 11.2.1.5 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ? 0 ? state to a logic ? 1 ? state while the smbus clock line is in a logic ? 1 ? state. when the ucs81003 detects an smbus stop bit, and it has been communicating with the smbus protocol, it will reset its client interface and prepare to receive further communications. 11.2.1.6 smbus timeout and idle reset the ucs81003 includes an smbus timeout feature. if the clock is held at logic ? 0 ? for t timeout , the device can time- out and reset the smbus interface. the smbus interface can also reset if both the clock and data lines are held at a logic ? 1 ? for t idle_reset . communication is restored with a start condition. this functionality defaults to disabled and can be enabled by clearing the dis_to bit in the emulation configuration register ( register 10-9 ). 11.2.2 smbus and i 2 c compatibility the major differences between smbus and i 2 c devices are highlighted in this section. for more information, refer to the smbus 2.0 and i 2 c specifications. ? ucs81003 supports i 2 c fast mode at 400 khz. this covers the smbus maximum time of 100 khz. ? minimum frequency for smbus communications is 10 khz. ? the smbus client protocol will reset if the clock is held at a logic ? 0 ? for longer than 30 ms. this time- out functionality is disabled by default in the ucs81003 and can be enabled by clearing the dis_to bit. i 2 c does not have a timeout. ? except when operating in sleep mode, the smbus client protocol will reset if both the clock and data lines are held at a logic ? 1 ? for longer than 200 s (idle condition). this function is disabled by default in the ucs81003 device and can be enabled by clearing the dis_to bit. i 2 c does not have an idle condition. ?i 2 c devices do not support the alert response address functionality (which is optional for smbus). ?i 2 c devices support block read and write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. the ucs81003 supports i 2 c formatting only.
ucs81003 ds20005334a-page 98 ? 2014 microchip technology inc. 11.2.3 smbus protocols the ucs81003 is smbus 2.0-compatible and supports write byte, read byte, send byte, and receive byte as valid protocols as shown in the following sections. all protocols in these sections use the convention in table 11-3 . 11.2.3.1 smbus write byte the write byte is used to write one byte of data to a specific register as shown in table 11-4 . 11.2.3.2 smbus read byte the read byte protocol is used to read one byte of data from the registers as shown in table 11-5 . 11.2.3.3 smbus send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in table 11-6 . 11.2.3.4 smbus receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g., set via send byte). this is used for consecutive reads of the same register as shown in table 11-7 . table 11-3: protocol format data sent to device data sent to the host data sent data sent table 11-4: write byte protocol start client address wr ack register address ack register data ack stop 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 0 -> 1 table 11-5: read byte protocol start client address wr ack register address ack start client address rd ack register data nack stop 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yy y 10xxh 10 -> 1 table 11-6: send byte protocol start client address wr ack register address ack stop 1 -> 0 yyyy_yyy 0 0 xxh 0 0 -> 1 table 11-7: receive byte protocol start client address rd ack register data nack stop 1 -> 0 yyyy_yyy 1 0 xxh 1 0 -> 1
? 2014 microchip technology inc. ds20005334a-page 99 ucs81003 11.2.4 i 2 c protocols the ucs81003 supports i 2 c block read and block write. the protocols listed below use the convention in table 11-3 . 11.2.4.1 block write the block write is used to write multiple data bytes to a group of contiguous registers as shown in table 11-8 . 11.2.4.2 block read the block read is used to read multiple data bytes from a group of contiguous registers as shown in table 11-9 . note: when using the block write protocol, the internal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. table 11-8: block write protocol start client address wr ack register address ack register data ack 1 ->0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1 note: when using the block read protocol, the internal address pointer will be automatically incremented after every data byte is received. it will wrap from ffh to 00h. table 11-9: block read protocol start client address wr ack register address ack start client address rd ack register data 1->0 yyyy_yyy 0 0 xxh 0 1 ->0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1
ucs81003 ds20005334a-page 100 ? 2014 microchip technology inc. 11.3 stand-alone operating mode stand-alone mode allows the ucs81003 to operate without active smbus/i 2 c communications. stand- alone mode can be enabled by connecting a pull-down resistor greater or equal to 47 k ? on the comm_sel/i lim pin as shown in ta bl e 11 - 1 . when the device is configured to operate in stand- alone mode, the fault handling and attach detection controls are determined via the latch and s0 pins as shown in table 11-10 . in the stand-alone operating mode, communications from and to the ucs81003 are limited to the pwr_en, em_en, m2, m1, alert# and a_det# pins. note: if it is necessary to connect the s0 or latch pins to v dd via a pull-up resistor, the pull-up resistor value should be 100 k ? in order to guarantee v ih specification. similarly, if it is necessary to connect the s0 or latch pins to gnd via a pull-down resistor, the pull-down resistor value should be 100 k ? in order to guarantee v il specification. table 11-10: stand-alone fault and attach detection selection latch pin s0 pin command low low no attach detection. auto-recovery upon error detection. low high attach detection in the detect power state. auto-recovery upon error detection. high low no attach detection. error states are latched and require host to change pwr_en control to recover from error state. high high attach detection in the detect power state. error states are latched and require host to change pwr_en control to recover from error state.
? 2014 microchip technology inc. ds20005334a-page 101 ucs81003 12.0 packaging information 12.1 package marking information 28-lead vqfn (5x5x0.9 mm) example legend: y year code (last digit of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code package country of origin pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 81003am c64c1a415 t415c64a kr ^^ 3 e 81003am nnnyww tywwnnna
ucs81003 ds20005334a-page 102 ? 2014 microchip technology inc. b a 0.10 c b 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 1 2 n top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.05 c microchip technology drawing c04-334a sheet 1 of 2 a (a3) 28x d e d1 e1 a1 d2 e2 28x b e k 28-lead very thin plastic quad flat pack, no lead package (pv) 5x5 mm body [vqfn] with rectangular exposed pad l 0.10 c a 2x 0.10 c b 2x 2x 0.10 c a 2x 4x ch
? 2014 microchip technology inc. ds20005334a-page 103 ucs81003 microchip technology drawing c04-334a sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b (a3) e l n 0.50 bsc 0.20 ref 0.50 0.18 0.80 0.00 0.23 0.60 0.85 0.01 millimeters min nom 28 0.70 0.30 0.90 0.05 max k- 0.20 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is punch singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 28-lead very thin plastic quad flat pack, no lead package (pv) 5x5 mm body [vqfn] molded cap width molded cap length with rectangular exposed pad d e2 d2 e 2.80 2.50 5.00 bsc 2.60 2.90 5.00 bsc 3.00 2.70 d1 e1 4.75 bsc 4.75 bsc corner chamfer ch 0.24 0.42 0.60
ucs81003 ds20005334a-page 104 ? 2014 microchip technology inc. recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 3.00 2.70 millimeters 0.50 bsc min e max 4.70 contact pad length (x28) contact pad width (x28) y1 x1 1.05 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing c04-2334a nom silk screen 1 2 28 c1 contact pad spacing 4.70 contact pad to center pad (x28) (g1) 0.475 ref c2 c1 x2 y2 x1 e y1 (g1) 28-lead very thin plastic quad flat, no lead package (pv) - 5x5 mm body [vqfn] with rectangular exposed pad ev ev ?v thermal via diameter v 0.30 thermal via pitch ev 1.00
? 2014 microchip technology inc. ds20005334a-page 105 ucs81003 appendix a: revision history revision a (september 2014) ? original release of this document.
ucs81003 ds20005334a-page 106 ? 2014 microchip technology inc. product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: ucs81003am: automotive usb port power controller with charger emulation tape and reel option: blank = standard packaging (tube or tray) r = tape and reel (1) package: c1a = very thin plastic quad flat, no lead package ? 5x5 mm body with rectangular exposed pad, 28-lead (vqfn) examples: a) UCS81003AM-C1A: 28-pin, 5x5 vqfn lead- free rohs compliant package. b) ucs81003amr-c1a: tape and reel, 28-pin, 5x5 vqfn lead- free rohs compliant package. part no. device -x x x package [x] (1) tape and reel note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability for the tape and reel option.
? 2014 microchip technology inc. ds20005334a-page 107 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-557-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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